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FPGA-CPU
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Search Results for "java"
Re: Re: Small CPUs in FPGAs [4 Articles]
John Kent - Aug 6 2008
Rick,
Do you really think there is a market for a cross platform processor
core ? I have not looked at the JOP, Java Oriented Processor, but if
that can support C as well as... 
Java JTAG API [6 Articles]
Kolja Sulimma - Jan 12 2005
I found the Java JTAG API that I was talking about.
It is called JavaScan and has been withdrawn.
http://www.jcp.org/en/jsr/detail?id=2
(inkludes example sour... Re: Re: Emulation of Processor [2 Articles]
Tomasz Sztejka - Dec 22 2003
--- Eng How Khoo <> wrote: > Hi Rob,
>
> May i ask for more information on how you implement the 6502? cos i
> am doing an emulator on 6502 also ....
> I plan... Ann: IO expansion with Ethernet chip
Martin Schoeberl - Dec 8 2002
Some weeks ago I announced an ACEX prototyping board. Now an IO expansion for this is available.
The board contains CS8900 Ethernet chip, voltage regulator and EMC... Java processor / RISC cpu [12 Articles]
Martin Schoeberl - Mar 18 2003
Hi Josh,
an answer on the list again. I don't think it's off-topic and we don't annoy
anybody. This Java Processor _is_ a fpga cpu. So why not discuss it here? ... Re: Strict P&R in Xilinx chips
- Dec 3 2001
Eric Laforest <> writes:
> Is it possible to generate a design that is explicitely placed and routed?
> (ie: this reg goes here, uses these tristate lines up to ... Hardware for exception handling [2 Articles]
Rob Finch - Mar 10 2003
Can anyone give me a good reference (URL) to information on hardware
support for exception handling as used in a language like Java or C++.
Thanks,
Rob
... Re: Help in compiler design.
Martin Schoeberl - Mar 20 2002
> I would be thankful if some one here cold give some idea
> on writing an assembler or compiler.
>
A simple assembler written in a good language (like Java with ... Re: Initial block ram contents
Christian Plessl - Jan 3 2002
> How do I initialize the block ram contents without going through the
> PAR process every time ? Could someone please point me to more info.
What kind of devic... Re: How about writing an FPGA processor with JHDL? [5 Articles]
Ben Franchuk - Mar 25 2002
Welson Sun wrote:
>
> Hi all,
>
> These days, I am looking at JHDL ( http://www.jhdl.org ), although
> it seems that there are a lot of issues to be sol... Re: multiCPUs + wide bus on FPGA [4 Articles]
Martin Schoeberl - Jul 15 2003
> 2. I would suuggest to go for the NIOS RISC processor from the
> Altera . It's provided by altera and it's free. Even the RTL
> Source is provided.
>
Is NIOS ... Re: ADC
Martin Schoeberl - Oct 14 2004
>> I am using Altera Quartus II ver4.0 tool - VHDL langauage.
>>Please any body guide me how to do ADC with/without using analog
>>related library..?
>>
>>Than... AD: ACEX 1K50 FPGA board clearance sale
Martin Schoeberl - Sep 9 2004
I have a few Altera ACEX 1K50 board for sale:
Each board contains:
ACEX EP1K50TC144-3
128 KB RAM
512 KB Flash (configuration and user data)
MAX EPM7032 for... Prototyping board for Altera ACEX
Martin Schoeberl - May 24 2002
I'm building a new board with Altera EP1K50 for my java processor (see www.jopdesign.com). I would like to split the cost for PCB, parts, board routing,... The board is... Re: Experiences with the Altera UP3-board and NiosII [2 Articles]
Martin Schoeberl - Feb 3 2005
> I was wondering if anyone has experiences using the Altera UP3-board
> with NiosII? Any comments are welcome. I'm looking for an
> educational board suitable fo... Re: transactional memory
fgruend - Feb 14 2007
examples from
http://tcc.stanford.edu/publications/tcc_pldi2006.pdf -- JAVA : public
int get (){
synchronized (this) {
while (!available)
wait();
available = false;
notifyAl... related to 16-bit fpga cpu development [5 Articles]
Umair siddiqui - Oct 11 2004
First of all thanks for reply.
Well I want to mimic the Mr.Gray's x16 and MIPS(as
discribed in "Computer Organization and Design
The Hardware/Software Interfa... Re: Dose Altera Nios support hardware-based multi-thread and how?
Martin Schoeberl - Apr 10 2004
> In Altera development kits ,I can't find the description about it.
> The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially,
> it has the sliding regis... Re: New Project
Martin Schoeberl - Nov 6 2004
Hi Can,
an interesting project. Perhaps you have already found it, but I want to
provide you a link to a Java processor in an FPGA:
http://www.jopdesign.com/... xr16vx in JHDL is running on chip
Mike Butts - Jun 10 2001
I have my implementation of xr16 in JHDL running reliably on
my Insight XC2S100 board. It's running a C program which is
echoing serial in to serial out, and also t... Ann: ALTERA prototyping board
Martin Schoeberl - Oct 27 2002
As there are so many boards for the Xilinx family I would like to support the Altera users.
The board contains everything needed for cpu designs:
ACEX 1K50 FPGA ... Re: Re: Microblaze In FPGA Virtex4 ML401?
Tommy Thorn - Jul 25 2007
Martin Schoeberl wrote:You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.
What in particular?
Alas, t... Choosing FPGA [2 Articles]
usertogo - Mar 23 2004
Hi Folks
I am new to this list and the FPGA world (not counting my experience
using PAL/GAL and some little Lattice ISP CPLD).
Obviously I am very excited abo... Re: FPGA DIMM module
Martin Schoeberl - Jul 29 2003
But I can see only a PCB without components. No price for assembled board?
Martin
--------------------------------------------------------
JOP - a Java Process... Summary of what's new at FPGA CPU News (www.fpgacpu.org)
Jan Gray - Sep 24 2000
00/09/24
Xilinx Student Edition 2.1i is shipping!
00/09/22
Site tweaked.
Separate application CPUs for 3G phones.
Xilinx acquires formal verification tools... Re: What are peoples opinion of the Altera Nios Processor?
Martin Schoeberl - Mar 18 2003
> > I'll be writing a paper in the next few weeks: a survey of commercially
and
> > freely available 32-bit RISC IP cores.
>
> Interssting. You may post a link ... CNets2000, a work in progress
Jan Gray - Aug 11 2000
THE RIGHT TOOL FOR THE JOB
To achieve near-optimal FPGA cores it is often necessary to control both
technology mapping and placement of the circuit -- and to do ... Re: Multiplying, MicroBlaze
Kolja Sulimma - Apr 10 2001
If you have a godd compiler you are right. According to HP, 95% of all
multiplies are constant multiplies that can be reduce to a few adds and
shifts. (The Java API... Re: Standalone system
Martin Schoeberl - Feb 3 2003
I can't resist to write some AD for my board:
Altera ACEX 1K50 FPGA
128 KB Ram
512 KB Flash (for configuration data and program memory)
MAX7032 PLD to load c... Re: Re: BGA prototyping
Martin Schoeberl - Feb 5 2004
That's cool ;-)
But not really the way how VCC/GND should be decoupled. I think you will
run into problems with such long wires to the caps.
Martin
---------... xr16vx in JHDL v1.0 is online
Mike Butts - Jun 30 2001
I've polished off the xr16vx microcontroller in JHDL, and
posted it, along with tools, tests and documentation:
http://www.easystreet.com/~mbutts/xr16vx_jhdl.htm... Re: Re: Xilinx vs Altera / Microblaze vs Nios??? [2 Articles]
Martin Schoeberl - Dec 15 2004
Mats and all,
as this discussion is going more in the direction of soft-core processors
I would like to add another option:
JOP: a Java processor soft-core ... RE: hardware cpu scheduler, pointers to papers? [3 Articles]
Jan Gray - Mar 22 2002
XYRON
> I just saw a reference to a company in Washington state that
> sells an ip core that has a hardware scheduler.
That would be Xyron Semi of Vancouve...