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FPGA-CPU

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Search Results for "verilog"

  

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Verilog simulator   [2 Articles]

Rob Finch - Aug 19 2000
I got the basic design verilog for a simple mpu (24 bit, which works quite nicely) done and I'd like to simulate it, but I figure it to be between 1200-1500 lines... Verilog simulator

Request for testers: SFL to Verilog converter

N S - Jun 15 2002
Hi, I wrote a SFL to Verilog converter program. The package is downloadable from my home page. The package has m65(6502 compatible), mz80( z80 semi-compatibl... Request for testers: SFL to Verilog converter

verilog vs Logiblox   [3 Articles]

Rob Finch - Aug 16 2000
I'm in the process of designing my very own mpu and I noticed that if I create an adder / subtracter using LogiBlox (Xilinx F1.5 software) it takes up alot less 4... verilog vs Logiblox

Execution unit in Verilog ?   [4 Articles]

Ben A. Abderazek - Nov 18 2004
Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-sty... Execution unit in Verilog ?

XSOC in Verilog and perhaps VHDL

Jan Gray, Gray Research LLC - Mar 17 2000
> From: Hernan Dario Sanchez Echeverri [mailto:] > some idea > doing this using VHDL ? I would like to help in any way. Thanks for your kind words and your ... XSOC in Verilog and perhaps VHDL

Verilog to VHDL tranlator   [3 Articles]

Avi Ben-Moshe - Sep 9 2002
Hi, Can you recommend on a GOOD Verilog to VHDL translator? Thanks, Avi ... Verilog to VHDL tranlator

Verilog code for an *bit Microprocessor   [2 Articles]

junaid_id1981 - Nov 27 2002
I am searching for verilog code for an 8-bit cpu. I'm trying to design my own 8 bit cpu with about 32-64 instructions based on 8085 cpu. Urgent help is ... Verilog code for an *bit Microprocessor

queries on verilog

Gurjit Chadha - Mar 12 2001
From Where can i download Verilog Tutorial,( books ,Manuals, etc) , Sample Codes, test benchs and Training manual . I hv Webpack suite with me. regards, ... queries on verilog

x86 16bit CPU

N S - Jun 4 2007
One of my graduated student agreed to open his design under the GPL. I put the sample code "x86FPGA package" under my web. http://www.ip-arch.jp/indexe.html It requires: s... x86 16bit CPU

Advice for a newbee, please!   [3 Articles]

ecstazi - Aug 19 2002
I'm starting to use FPGAs and I'm going to use Verilog for programming. What i'm search are informations, samples code, examples and other stuff regarding FPGA ... Advice for a newbee, please!

Re: POP-11 (PDP-11/40 in an FPGA)   [6 Articles]

Eric Smith - Aug 17 2007
Scott wrote: > I came across this old posting for the POP-11, but the original > URL no longer works. I'd really like to get the > VHDL source code for the POP-11 project if ... Re: POP-11 (PDP-11/40 in an FPGA)

VHDL and Verilog   [5 Articles]

Jin Yan - Feb 25 2003
Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry? Or which language is suitable to ... VHDL and Verilog

OT: verilog arrays   [3 Articles]

Rob Finch - Jan 22 2005
Does anyone know how to pass arrays to a module in Verilog ? I tried this as a test but it doesn't work: module arrayTest(s, a, o); input [2:0] s; input ... OT: verilog arrays

6502 Coding in Verilog

Eng How Khoo - Oct 20 2003
Hi all, Can someone recommend some website with example on existing microprocessor coding in Verilog and the steps needed to complete the coding. If got s... 6502 Coding in Verilog

Alpha or Alpha-like processor Verilog code

Ben A. Abderazek - Oct 22 2004
Hello Helpers, Does any one have or know a Verilog source code of Alpha 21164 (or Alpha -like) processor?. Many thanks for your help, /Ben UEC, IS, Jap... Alpha or Alpha-like processor Verilog code

verilog to vhdl   [4 Articles]

eesha_78 - Mar 12 2003
i'm very new in this area. i want to know how to convert from verilog to vhdl language..for example assign a= &b[7:0]; assign c= |d[7:0]; when i try to c... verilog to vhdl

I want to join any RISC processor design in Verilog HDL.   [2 Articles]

Ben A. Abderazek - May 14 2004
Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC processor in Verilog HDL. Regards, /... I want to join any RISC processor design in Verilog HDL.

XSOCV   [2 Articles]

Dan Crowl - Apr 24 2000
Jan, XSOCV rebuilt and downloaded (from NT4.0) with only one "scare" (execution tight-looped the first time, but I was unable to get a repeat after resetting t... XSOCV

FW: Verilog simulator   [2 Articles]

J O - Nov 26 2006
Hello I want to continue exploration of cpu archtectures in my past time and wondered if anyone knew of a low cost verilog simulator that i could purchase for home use ? ... FW: Verilog simulator

Suggestions re: Free Tools

rtstofer - Aug 24 2007
The problem with newbies such as myself is that not only don't they know anything, they don't even suspect! I have been using WebPack ISE for about 5 years and it has the adva... Suggestions re: Free Tools

LEON Verilog simulation   [3 Articles]

howlingmadwilger - Nov 1 2002
I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year project titled "Writing an instru... LEON Verilog simulation

Re: VHDL and Verilog... the answer?   [4 Articles]

Friman Sanchez Castaņo - Feb 25 2003
Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is better: Verilog or VHDL?". But really I... Re: VHDL and Verilog... the answer?

Help please   [8 Articles]

kalemanav - Aug 2 2002
Hi, Quick question. Can anyone please let me know if I can generate a clock with more frequency than input clock from a synthesisable verilog module.I appreciat... Help please

Calling a verilog-like package from VHDL   [2 Articles]

shaik afzal - May 28 2003
Hi all, Hope this is not an off-topic query. We have a set of VHDL Design files(Say VHDL1.Vhd,VHDL2.vhd etc.) and a VHDL Package(VHDL_pack.vhd) file. V... Calling a verilog-like package from VHDL

Need some advice on 6502 project

enghow1268 - Oct 1 2003
Hello everyone, My name is eng how, final year student from electrical and electornic engineering. Currently i'm doing on my final year project on 6502 emula... Need some advice on 6502 project

v6502   [4 Articles]

- Mar 9 2001
I started working on a verilog version of the 6502 processor yesterday. I handcrafted a state machine based on observations of opcode patterns and knowledge of th... v6502

digging out

Jan Gray - Mar 10 2001
Just a brief message tonight, more in a day or two. I updated the soc/gr0040 paper with the missing ram16x16d appendix, and built a little kit with the extracted... digging out

RE: Found link to Veriwell executable

Jan Gray - Aug 17 2000
Thank you, very helpful. Well, I was about to push this up to the web site: " Veriwell sightings In the XSOC Getting Started Guide, I lament that I was unab... RE: Found link to Veriwell executable

Inferred Priority Encoder In VHDL   [5 Articles]

rtstofer - Nov 28 2007
Consider something like: result ... Inferred Priority Encoder In VHDL

How design a FIFO in Verilog?   [2 Articles]

xvibe - Aug 20 2002
Can you explain me how to design a FIFO in Verilog? The FIFO that I'm talking about is of this type: ------------------------------- | | ---| DataIN Da... How design a FIFO in Verilog?

File io operations in Verilog

satya_1729 - Dec 26 2002
Hi All, I am new to Verilog. I used VHDL for 1 year. Currently i am facing a problem in writing test benches in Verilog. Currently my problem is reading a fil... File io operations in Verilog

Pipelined Processor and Buffers   [8 Articles]

Ben A. Abderazek - Oct 13 2004
Dear Helpers, I am implementing an FPGA pipelined processor that is expected to fetch and execute 2 inst/cycle. I want to implement buffers to separate eac... Pipelined Processor and Buffers

stoopid newbie verilog question--please help   [2 Articles]

Tom Kerrigan - Nov 19 2000
I've been working on my CPU and I just can't get the ALU to "build." The Verilog for the ALU is below. Xilinx complains that register C has both active and trist... stoopid newbie verilog question--please help

anyone has ps2 keyboard controller cores?   [3 Articles]

cationebox - Mar 31 2005
can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilo... anyone has ps2 keyboard controller cores?

Re: Inferred Priority Encoder In VHDL   [2 Articles]

Charles Steinkuehler - Nov 28 2007
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 rtstofer wrote: > The Verilog might look like: > > assign result = (sig1 ? a : 1'b0) | > (sig2 ? b : 1'b0) | > (sig3 ... Re: Inferred Priority Encoder In VHDL

HDL for FFT

hadi khani - May 6 2002
Hi, Does anybody have or know a free HDL(VHDL,Verilog) for of Parallel or FFT processor? Thanks. __________________________________________________... HDL for FFT

z80 cpu

- Aug 6 2000
Hi, For implementing a z80 cpu in an FPGA, I need the verilog or VHDL behavioral description of this cpu. Does anybody have anything to help me? Thank You.... z80 cpu
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