An Engineer's Guide to the LPC2100 Series
This book is intended as a hands-on guide for anyone planning to use the Philips LPC2000 family of microcontrollers in a new design. It is laid out both as a reference book and as a tutorial. It is assumed that you have some experience in programming microcontrollers for embedded systems and are familiar with the C language. The bulk of technical information is spread over the first four chapters, which should be read in order if you are completely new to the LPC2000 and the ARM7 CPU.
Choosing An Ultralow-Power MCU
This application report describes how to compare ultralow-power MCUs. It discusses the key differences between popular low-power MCUs and how to interpret features and specifications and apply them to application requirements
Interrupts, Low Power Modes and Timer A
This document contains a lot of what you need to know to get the most out of the MSP430. The MSP430 line is renowned for it's low power usage, and to really utilize it well you have to architect your software to be an interrupt driven device that utilizes the low power modes.
PID Without a PhD
PID (proportional, integral, derivative) control is not as complicated as it sounds. Follow these simple implementation steps for quick results.
Reed-Solomon Error Correction
[Best paper on Reed-Solomon error correction I have ever read -- and it's from the BBC!] Reed-Solomon error correction has several applications in broadcasting,in particular forming part of the specification for the ETSI digital terrestrial television standard, known as DVB-T. Hardware implementations of coders and decoders for Reed-Solomon error correction are complicated and require some knowledge of the theory of Galois fields on which they are based. This note describes the underlying mathematics and the algorithms used for coding and decoding,with particular emphasis on their realisation in logic circuits. Worked examples are provided to illustrate the processes involved.
Memory allocation in C
This article is about dynamic memory allocation in C in the context of embedded programming. It describes the process of dynamically allocating memory with visual aids. The article concludes with a practical data communications switch example which includes a sample code in C.
Red Hat Linux - The Complete Reference
This book identifies seven major Linux topics: basic setup, environments and applications, the Internet, servers, administration, and network administration. These topics are integrated into the different ways Red Hat presents its distribution: as a desktop workstation, network workstation, server, and development platform
Essential Linux Device Drivers
This book is about writing Linux device drivers. It covers the design and development of major device classes supported by the kernel, including those I missed during my Linux-on-Watch days. The discussion of each driver family starts by looking at the corresponding technology, moves on to develop a practical example, and ends by looking at relevant kernel source files. Before foraying into the world of device drivers, however, this book introduces you to the kernel and discusses the important features of 2.6 Linux, emphasizing those portions that are of special interest to device driver writers.
CPU Memory - What Every Programmer Should Know About Memory
As CPU cores become both faster and more numerous, the limiting factor for most programs is now, and will be for some time, memory access. Hardware designers have come up with ever more sophisticated memory handling and acceleration techniques–such as CPU caches–but these cannot work optimally without some help from the programmer. Unfortunately, neither the structure nor the cost of using the memory subsystem of a computer or the caches on CPUs is well understood by most programmers. This paper explains the structure of memory subsystems in use on modern commodity hardware, illustrating why CPU caches were developed, how they work, and what programs should do to achieve optimal performance by utilizing them.
Stop Guessing – Trace Visualization for RTOS Firmware Debugging
Some decades ago, the embedded industry shifted focus from assembly to C programming. Faster processors and better compilers allowed for raising the level of abstraction in order to improve development productivity and quality. We are now in the middle of a new major shift in firmware development technology. The increasing use of real-time operating systems (RTOS) represents the third generation of embedded software development. By using an RTOS, you introduce a new abstraction level that enables more complex applications, but not without complications.
Improving Battery Management System Performance and Cost with Altera FPGAs
The purpose of this white paper is to evaluate improvements to Battery Management System (BMS) performance and cost with Altera® FPGAs. In many high-voltage battery systems, including electric vehicles, grid attached storage and industrial applications, the battery is a significant portion of the system cost, and needs to be carefully managed by a BMS to maximize battery life and to optimize charging and discharging performance. This white paper presents the BMS functional requirements for these applications and outlines existing BMS architectures. Key BMS architectural challenges are discussed and opportunities for Altera devices are identified. For each of these opportunities, the performance and cost of the existing solution are compared with Altera FPGA solutions. Altera devices provide architectural flexibility, scalability, customization, performance improvements, and system cost savings in BMS applications.
A Multithreaded Real-time Robot for Embedded Design Space Exploration
This thesis introduces an autonomous robot platform for real-time scheduling exper- imentation and benchmark suite to evaluate real-time optimizations and apply modern task scheduling methods. It makes two contributions. First, it presents a reference hardware and software design for a line-following, obstacle-avoiding and maze-solving robot. This robot is based on a small commercially-available product. The software is structured as a multithreaded real- time system for use in evaluating scheduling approaches for cost-sensitive and resource- constrained applications. Second, it provides a detailed design space exploration showing the costs (processor speed and memory) of di erent scheduling approaches (static vs. dynamic and non-preemptive vs. preemptive). It also measures and analyzes each task's timing information and explores the mini- mum microcontroller clock speed under di erent scheduling approaches.
Transforming 64-Bit Windows to Deliver Software-Only Real-Time Performance
Next-generation industrial, vision, medical and other systems seek to combine highend graphics and rich user interfaces with hard real-time performance, prioritization and precision.Today’s industrial PCs running 64-bit Windows, complemented by a separate scheduler on multicore multiprocessors, can deliver that precise real-time performance on software-defined peripherals.
A Guide to Approximations
Most embedded processors don’t know how to compute trig and other complex functions. Programming in C we’re content to call a library routine that does all of the work for us. Unhappily this optimistic approach often fails in real time systems where size, speed and accuracy are all important issues. The compiler’s runtime package is a one-size-fits-all proposition. It gives a reasonable trade-off of speed and precision. But every embedded system is different, with different requirements. In some cases it makes sense to write our own approximation routines. Why?
Consistent Overhead Byte Stuffing
Byte stuffing is a process that transforms a sequence of data bytes that may contain ‘illegal’ or ‘reserved’ values into a potentially longer sequence that contains no occurrences of those values. The extra length is referred to in this paper as the overhead of the algorithm. To date, byte stuffing algorithms, such as those used by SLIP [RFC1055], PPP [RFC1662] and AX.25 [ARRL84], have been designed to incur low average overhead but have made little effort to minimize worst case overhead. Some increasingly popular network devices, however, care more about the worst case. For example, the transmission time for ISM-band packet radio transmitters is strictly limited by FCC regulation. To adhere to this regulation, the practice is to set the maximum packet size artificially low so that no packet, even after worst case overhead, can exceed the transmission time limit. This paper presents a new byte stuffing algorithm, called Consistent Overhead Byte Stuffing (COBS), that tightly bounds the worst case overhead. It guarantees in the worst case to add no more than one byte in 254 to any packet. Furthermore, the algorithm is computationally cheap, and its average overhead is very competitive with that of existing algorithms.
Introduction to Embedded Systems
This is the first chapter in the book Embedded Systems Hardware for Software Engineers.
Topics in Secure Embedded System Design
Pervasive networks have led to widespread use of embedded systems, like cell phones, PDAs, RFIDs etc., in increasingly diverse applications. Many of these embedded system appli- cations handle sensitive data (e.g., credit card information on a mobile phone/PDA) or perform critical functions (e.g., medical devices or automotive electronics), and the use of security protocols is imperative to maintain con dentiality, integrity and authentication of these applications. Typically embedded systems have low computing power and nite energy supply based on a battery, and these factors are at odds with the computationally intensive nature of the cryptographic algorithms underlying many security protocols. In addition, secure embedded systems are vulnerable to attacks, like physical tampering, malware and side-channel attacks. Thus, design of secure embedded systems is guided by the following factors: small form factor, good performance, low energy consumption (and, thus,longer battery life), and robustness to attacks. This thesis presents our work on tackling three issues in the design of secure embedded systems: energy consumption, performance and robustness to side-channel attacks. First, we present our work on optimizing the energy consumption of the widely employed secure sockets layer (SSL) protocol running on an embedded system. We discuss results of energy analysis of various cryptographic algorithms, and the manner in which this information can be used to adapt the operation of SSL protocol to save energy. Next, we present results of our experiments on optimizing the performance of Internet protocol security (IPSec) protocol on an embedded processor. Depending on the mode of operation, the IPSec computation is dominated by cryptographic or non-cryptographic processing. We demonstrate how both these components of the IPSec protocol can be optimized by leveraging the extensible and con gurable features of an embedded processor. Next, we introduce a satisfability-based framework for enabling side-channel attacks on cryptographic software running on an embedded processor. This framework enables us to identify variables in the software implementations which result in the disclosure of the secret key used. Thus, security of software implementations can be improved by better protection of these identified variables. Finally, we conclude by introducing a novel memory integrity checking protocol that has much lower communication complexity than existing Merkle tree-based protocols while incurring a modest price in computation on the processor. This scheme is based on Toeplitz matrices, and can be very efficiently realized on embedded systems with hardware extensions for bit matrix operations.
Enhanced Sample Rate Mode Measurement Precision
The low-noise system architecture and the tailored frequency response employed in the HDO4000A, HDO6000A, HDO8000A and MDA800A series provides the foundation for enhancing ADC sample rates through additional techniques. In this case, carefully constructed filters combined with a pristine front-end amplifier and a frequency response carefully limited to 1 GHz provide the opportunity to provide more measurement precision than would otherwise be possible. The technique utilized to achieve higher measurement precision is interpolation, and this technique is used by default as an Enhanced Sample Rate up to 10 GS/s. By integrating the Enhanced Sample Rate functionality with the normal Timebase controls for Sample Rate, Time and Acquisition Memory adjustment, the oscilloscopes are optimized for best waveform signal fidelity in all situations.
Demystifying digital signal processing (DSP) programming: The ease in realizing implementations with TI DSPs
Introduced by Texas Instruments over thirty years ago, the digital signal processor (DSP) has evolved in its implementation from a standalone processor to a multicore processing element and has continued to extend in its range of applications. The breadth of software development tools for the DSP has also expanded to accommodate diverse sets of programmers. From small, low power, yet “smart” devices with applications such as voice and image recognition, to multicore, high-performance compute platforms performing real-time data analytics, the opportunities to achieve the low-power processing efficiencies of DSPs are nearly endless. The TI DSP has benefited from a relatively unique tool suite evolution making it easy and effective for the general programmer and the signal processing expert alike to quickly develop their application code. This paper addresses how TI DSP users are able to achieve the high performance afforded by the TI DSP architecture, in an efficient, easy-to-use development environment.
