Building an embedded system from an idea to a product is a slow and expensive process requiring a lot of expertise. Depending on the developer’s expertise, the required quantity and price level of the final product, and the time and money available for development, the developer can build a device from different granularity of components, ranging from ready-made platforms, kits, and modules to individual components. Generally, solutions requiring less expertise, time and money produce products with higher production costs. The main contribution of this thesis is the EOC (Embedded Object Concept) and Atomi II Framework. EOC utilizes common object-oriented methods used in software by applying them to small electronic modules, which create complete functional entities. The conceptual idea of the embedded objects is implemented with the Atomi II framework, which contains several techniques for making the EOC a commercially feasible implementation. The EOC and the Atomi II Framework decreases the difficulty level of making embedded systems by enabling a use of ready-made modules to build systems. It enables automatic conversion of a device made from such modules into an integrated PCB, lowering production costs compared to other modular approaches. Furthermore, it also enables an automatic production tester generation due to its modularity. These properties lower the number of skills required for building an embedded system and quicken the path from an idea to a commercially applicable device. A developer can also build custom modules of his own if he possesses the required expertise. The test cases demonstrate the Atomi II Framework techniques in real world applications, and demonstrate the capabilities of Atomi objects. According to our test cases and estimations, an Atomi based device becomes approximately 10% more expensive than a device built from individual components, but saves up to 50% time, making it feasible to manufacture up to 10-50k quantities with this approach.
Pervasive networks have led to widespread use of embedded systems, like cell phones, PDAs, RFIDs etc., in increasingly diverse applications. Many of these embedded system appli- cations handle sensitive data (e.g., credit card information on a mobile phone/PDA) or perform critical functions (e.g., medical devices or automotive electronics), and the use of security protocols is imperative to maintain condentiality, integrity and authentication of these applications. Typically embedded systems have low computing power and nite energy supply based on a battery, and these factors are at odds with the computationally intensive nature of the cryptographic algorithms underlying many security protocols. In addition, secure embedded systems are vulnerable to attacks, like physical tampering, malware and side-channel attacks. Thus, design of secure embedded systems is guided by the following factors: small form factor, good performance, low energy consumption (and, thus,longer battery life), and robustness to attacks. This thesis presents our work on tackling three issues in the design of secure embedded systems: energy consumption, performance and robustness to side-channel attacks. First, we present our work on optimizing the energy consumption of the widely employed secure sockets layer (SSL) protocol running on an embedded system. We discuss results of energy analysis of various cryptographic algorithms, and the manner in which this information can be used to adapt the operation of SSL protocol to save energy. Next, we present results of our experiments on optimizing the performance of Internet protocol security (IPSec) protocol on an embedded processor. Depending on the mode of operation, the IPSec computation is dominated by cryptographic or non-cryptographic processing. We demonstrate how both these components of the IPSec protocol can be optimized by leveraging the extensible and congurable features of an embedded processor. Next, we introduce a satisfability-based framework for enabling side-channel attacks on cryptographic software running on an embedded processor. This framework enables us to identify variables in the software implementations which result in the disclosure of the secret key used. Thus, security of software implementations can be improved by better protection of these identified variables. Finally, we conclude by introducing a novel memory integrity checking protocol that has much lower communication complexity than existing Merkle tree-based protocols while incurring a modest price in computation on the processor. This scheme is based on Toeplitz matrices, and can be very efficiently realized on embedded systems with hardware extensions for bit matrix operations.
Wireless embedded networks have matured beyond academic research as industry now considers the advantages of using wireless sensors. With this growth, reliability and real-time demands increase, thus timing becomes more and more relevant. In this dissertation, we focus on the development of highly stable, low-power clock systems for wireless embedded systems. Wireless embedded networks, due to their wire-free nature, present one of the most extreme power budget design challenges in the ﬁeld of electronics. Improvements in timing can reduce the energy required to operate an embedded network. However, the more accurate a time source is, the more power it consumes. To comprehensively address the time and power problems in wireless embedded systems, this dissertation studies the exploitation of dual-crystal clock architectures to combat eﬀects of temperature induced frequency error and high power consumption of high-frequency clocks. Combining these architectures with the inherent communication capabilities of wireless embedded systems, this dissertation proposes two new technologies; (1) a new time synchronization service that automatically calibrates a local clock to changes in temperature; (2) a high-low frequency timer that allows a duty-cycled embedded system to achieve ultra low-power sleep, while keeping ﬁne granularity time resolution oﬀered only by high power, high frequency clocks.
This book addresses a wide spectrum of research topics of embedded systems, including parallel computing, communication architecture, application-specific systems, and embedded systems projects.
Byte stuffing is a process that transforms a sequence of data bytes that may contain ‘illegal’ or ‘reserved’ values into a potentially longer sequence that contains no occurrences of those values. The extra length is referred to in this paper as the overhead of the algorithm. To date, byte stuffing algorithms, such as those used by SLIP [RFC1055], PPP [RFC1662] and AX.25 [ARRL84], have been designed to incur low average overhead but have made little effort to minimize worst case overhead. Some increasingly popular network devices, however, care more about the worst case. For example, the transmission time for ISM-band packet radio transmitters is strictly limited by FCC regulation. To adhere to this regulation, the practice is to set the maximum packet size artificially low so that no packet, even after worst case overhead, can exceed the transmission time limit. This paper presents a new byte stuffing algorithm, called Consistent Overhead Byte Stuffing (COBS), that tightly bounds the worst case overhead. It guarantees in the worst case to add no more than one byte in 254 to any packet. Furthermore, the algorithm is computationally cheap, and its average overhead is very competitive with that of existing algorithms.
This thesis introduces an autonomous robot platform for real-time scheduling exper- imentation and benchmark suite to evaluate real-time optimizations and apply modern task scheduling methods. It makes two contributions. First, it presents a reference hardware and software design for a line-following, obstacle-avoiding and maze-solving robot. This robot is based on a small commercially-available product. The software is structured as a multithreaded real- time system for use in evaluating scheduling approaches for cost-sensitive and resource- constrained applications. Second, it provides a detailed design space exploration showing the costs (processor speed and memory) of dierent scheduling approaches (static vs. dynamic and non-preemptive vs. preemptive). It also measures and analyzes each task's timing information and explores the mini- mum microcontroller clock speed under dierent scheduling approaches.