strange register behavior in Verilog blocks under Quartus II

Started by lionheart_99_de in FPGA-CPU14 years ago

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th


Wishbone comments

Started by Martin Schoeberl in FPGA-CPU13 years ago 7 replies

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes...

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes it not the best choice for SoC interconnect. The Wishbone interface specification is still in the tradition of microcomputer or backplane busses. However, for a SoC interconnect, which is usually point-to-point, this is


Memory Management

Started by Rob Finch in FPGA-CPU14 years ago 3 replies

What kind of memory management features do the NIOS / Microblaze offer ? What would be appropriate for SoC systems ? I've...

What kind of memory management features do the NIOS / Microblaze offer ? What would be appropriate for SoC systems ? I've been working on a simple segmented system, plus a bitmap for execute / write able memory. But I'm thinking maybe I'm making things too complex. I


I got it working !!!

Started by Rob Finch in FPGA-CPU14 years ago 2 replies

I got it working !!!! An SoC with cpu, video controller, uart, and a few other peripherals. The cpu is similar in concept...

I got it working !!!! An SoC with cpu, video controller, uart, and a few other peripherals. The cpu is similar in concept to the gr0040's. The full featured 32 bit cpu is only 620 LUTs! The ram access is pipelined for performance. Runs at 28.636MHz ! Powers up, displ


Xilinx vs Altera / Microblaze vs Nios???

Started by Mats Brorsson in FPGA-CPU14 years ago 14 replies

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards


bc6502 running EnhBASIC

Started by rtfinch36 in FPGA-CPU16 years ago 2 replies

I've managed to get Lee Davison's EnhBASIC working on my 6502 SoC. (The hard part was getting the 6502 core to work properly.)...

I've managed to get Lee Davison's EnhBASIC working on my 6502 SoC. (The hard part was getting the 6502 core to work properly.) Lee's EnhBASIC was a snap to make use of. I've reduced the size of the core down to about 650 LUTs, so it should easily fit in a 10k device (although I h


Paul Metzgen on multiplexers and the NIOS II pipeline

Started by Tommy Thorn in FPGA-CPU11 years ago 5 replies

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen:...

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen: http://www.cs.tut.fi/soc/Metzgen04.pdf (I wish I had attended this talk). Among other things, he shows how on Stratix/Cyclone, a single LE can implement (assuming sclear and sload is shared between all LE in a LAB) if (sclear) q


Butterfly processor info

Started by Rob Finch in FPGA-CPU14 years ago

Info on the processor used in my SoC: http://www.birdcomputer.ca/Cores/B utterfly32_info.html I have more docs on...

Info on the processor used in my SoC: http://www.birdcomputer.ca/Cores/B utterfly32_info.html I have more docs on the way. It just takes time to put together good documentation.


[ANN] Altera Cyclone EP1C12 FPGA Board

Started by Martin Schoeberl in FPGA-CPU14 years ago

The successful Cyclone EP1C6 FPGA module is now available with the larger Cyclon EP1C12. The board is an ideal module for SoC design...

The successful Cyclone EP1C6 FPGA module is now available with the larger Cyclon EP1C12. The board is an ideal module for SoC design with soft-core CPUs such as NIOS or JOP. Additional to the FPGA it conatins a three stage memory hirarchy: Fast asynchron memory as main memory.


More Butterfly Info

Started by Rob Finch in FPGA-CPU14 years ago

I plan to keep the following webpage updated with info on the Butterfly SoC. ...

I plan to keep the following webpage updated with info on the Butterfly SoC. http://www.birdcom puter.ca/Projects/PrjButterflySoC/Butterfly_SoC.html There is a bitfile available