Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N) -

Started by mani...@gmail.com in FPGA-CPU8 years ago

> > Hello, > > Does somebody work with DC-VIDEO-TVP5146N Altera kit > >...

> > Hello, > > Does somebody work with DC-VIDEO-TVP5146N Altera kit > > (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? > > I try to connect DC-VIDEO-TVP5146N to DK-NIOS-2S60N (http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html) via SantaCruz interface. In > > fact I use NIOS with OpenCores i2c master to connect to TVP5146 video adc > > via i2c interface.


Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)

Started by gmdi...@gmail.com in FPGA-CPU8 years ago

Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to...

Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to connect DC-VIDEO-TVP5146N to DK-NIOS-2S60N (http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html) via SantaCruz interface. In fact I use NIOS with OpenCores i2c master to connect to TVP5146 video adc via i2c interface. The problem is tha...


Unable to generate NIOS II

Started by syyang85 in FPGA-CPU10 years ago 1 reply

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios...

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios II system made by Altera. But i get the following error when I try to generate it. What error is this? On the other hand, what is the best way to save a stream of data into SDRAM? or would it be better if I made a soft memory for this purpose? Rega...


LEON-2 softCore in Altera's Quartus

Started by palomino778 in FPGA-CPU16 years ago 1 reply

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and...

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and would appreciate any pointers.


Good FPGA developmnet Board

Started by Ben A. Abderazek in FPGA-CPU15 years ago 1 reply

Hello helpers, I need to buy an FPGA to implement a 32-bit RISC-like processor. I found this board: APEX PCI Development Kit...

Hello helpers, I need to buy an FPGA to implement a 32-bit RISC-like processor. I found this board: APEX PCI Development Kit (APEX 20KE) from Altera ( http://www.altera.com/produc ts/devkits/kit-dev_platforms.jsp


Xilinx vs Altera / Microblaze vs Nios???

Started by Mats Brorsson in FPGA-CPU14 years ago 14 replies

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards


Re: Query on FPGA testing after configure it.

Started by juendme in FPGA-CPU13 years ago

The best way to test an FPGA design running on the chip is to use one of the on-chip analyzers. If you're using Altera's FPGAs, try ...

The best way to test an FPGA design running on the chip is to use one of the on-chip analyzers. If you're using Altera's FPGAs, try SignalTap II ( http://www.altera.com/products/software/products/quartus2/verification/signaltap2/sig-in dex.html ). If you're usin


Experiences with the Altera UP3-board and NiosII

Started by Mats Brorsson in FPGA-CPU13 years ago 3 replies

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking...

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking for an educational board suitable for microprocessor designs and this seems to have the right peripherals.


Beginning with FPGAs

Started by rtstofer in FPGA-CPU9 years ago 2 replies

Altera and Arrow have joint ventured a neat little Hitex USB based FPGA evaluation USB stick...

Altera and Arrow have joint ventured a neat little Hitex USB based FPGA evaluation USB stick for $49 http://www.altera.com/b/nios-bemicro-evaluation-kit.html?GSA_pos=3&WT.oss_r=1&WT.oss=bemicro It's a pretty neat evaluation board and the lab documents have you build a NIOS II system and use the GNU toolchain to write some C code for it. Everything is included. Well, except that most of the...


altera cyclone bitstream format ?

Started by __--__ in FPGA-CPU15 years ago

** I am attempting to get information about the altera bitstream format ** I have already read ...

** I am attempting to get information about the altera bitstream format ** I have already read http://opencollector.org/news/Bitstream/ I wanted to make sure I wasn't missing something, is the information fo


Nios 2 announcements

Started by Jan Gray in FPGA-CPU14 years ago

See http://www.altera.com/ products/ip/processors/nios2/ni2-index.html. Very interesting. I applaud the spectrum of...

See http://www.altera.com/ products/ip/processors/nios2/ni2-index.html. Very interesting. I applaud the spectrum of implementation choices and the D-MIPS one-upsmanship. :-) Such versatile soft co


FPGA to ARM7 shared memory concept via wishbone.

Started by djam...@gmail.com in FPGA-CPU8 years ago 5 replies

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration...

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ARM processor (running uLinux), -- a 16M Synchronous DRAM (connected to FPGA and ARM) -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to...


Dose Altera Nios support hardware-based multi-thread and how?

Started by qfmyue in FPGA-CPU14 years ago 1 reply

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU...

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial ma


ADC

Started by sukumar in FPGA-CPU14 years ago 4 replies

Hi all, I am using Altera Quartus II ver4.0 tool - VHDL langauage. Please any body guide me how to do ADC with/without...

Hi all, I am using Altera Quartus II ver4.0 tool - VHDL langauage. Please any body guide me how to do ADC with/without using analog related library..? Thank you, --sukumar


What are peoples opinion of the Altera Nios Processor?

Started by barrem23 in FPGA-CPU15 years ago 5 replies

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor? ...

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor?


SOPC TMS370

Started by leonherbers in FPGA-CPU14 years ago

Hello, I'm working on the cloning of the TMS370 microcontroller by Texas Instruments, in an Altera Cyclone Device. I'd...

Hello, I'm working on the cloning of the TMS370 microcontroller by Texas Instruments, in an Altera Cyclone Device. I'd realy like to know if there are others on this planet wo've been working on the TMS also. E.g. makeing of VHDL codes, IP cores etc. etc.


Flattened BGA's ?

Started by David Gregory in FPGA-CPU10 years ago 3 replies

Is it normal when purchasing Programmable Logic Devices (Xilinx / Altera) that are brand new, 08+ date codes, and factory sealed, for them to...

Is it normal when purchasing Programmable Logic Devices (Xilinx / Altera) that are brand new, 08+ date codes, and factory sealed, for them to arrive with some slightly flattened BGA's and dinged discolored edges? These can be barely seen with the naked eye but definitely under our superscope. If it is normal what is the cause? Any help out there is appreciated. Thanks, Dave _________...


Please help me with the XR-16 design work

Started by Yi Zhang in FPGA-CPU16 years ago 1 reply

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the...

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the clock cycles of a specific C program). Those who also do the similiar work of multi-cpu (XR-16) design: please give me your kind advice and share some useful ex


Re: Low cost Altera board

Started by Martin Schoeberl in FPGA-CPU13 years ago 9 replies

> > I'm interested in the equivalence as well. My Z80 CP/M project > takes 2992 of the 6144 available LUTS in a XC2S300E Xilinx FPGA. ...

> > I'm interested in the equivalence as well. My Z80 CP/M project > takes 2992 of the 6144 available LUTS in a XC2S300E Xilinx FPGA. > The 'equivalent gate count' is 259,353 + 4704 for JTAG. I'm still > not clear about the definition of 'equivalent gate count' as it is > about 264k of the '300k' gate device, about 88%. On a LUT basis the


Eagle Library part Altera Cyclone EP1C12 or 6

Started by usertogo in FPGA-CPU13 years ago

Hi I am wondering if there is a more complete libray for the 240 pin PQFP version of this EP1C12 FPGA that sombody would share? ...

Hi I am wondering if there is a more complete libray for the 240 pin PQFP version of this EP1C12 FPGA that sombody would share? The one that comes with the free eagle PCB package allready contains the padstack and I am hoping to save the work of making a symbol for now (eve