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Unable to generate NIOS II

Started by syyang85 in FPGA-CPU16 years ago 1 reply

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios...

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios II system made by Altera. But i get the following error when I try to generate it. What error is this? On the other hand, what is the best way to save a stream of data into SDRAM? or would it be better if I made a soft memory for this purpose? Rega...


LEON-2 softCore in Altera's Quartus

Started by palomino778 in FPGA-CPU21 years ago 1 reply

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and...

Has anyone ever tried to compile the LEON in Altera's Quartus II software? I'm having some trouble getting everything set up and would appreciate any pointers.


Xilinx vs Altera / Microblaze vs Nios???

Started by Mats Brorsson in FPGA-CPU19 years ago 14 replies

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards


Experiences with the Altera UP3-board and NiosII

Started by Mats Brorsson in FPGA-CPU19 years ago 3 replies

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking...

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking for an educational board suitable for microprocessor designs and this seems to have the right peripherals.


altera cyclone bitstream format ?

Started by __--__ in FPGA-CPU21 years ago

** I am attempting to get information about the altera bitstream format ** I have already read ...

** I am attempting to get information about the altera bitstream format ** I have already read http://opencollector.org/news/Bitstream/ I wanted to make sure I wasn't missing something, is the information fo


FPGA to ARM7 shared memory concept via wishbone.

Started by djam...@gmail.com in FPGA-CPU14 years ago 5 replies

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration...

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ARM processor (running uLinux), -- a 16M Synchronous DRAM (connected to FPGA and ARM) -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to...


Dose Altera Nios support hardware-based multi-thread and how?

Started by qfmyue in FPGA-CPU20 years ago 1 reply

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU...

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial ma


What are peoples opinion of the Altera Nios Processor?

Started by barrem23 in FPGA-CPU21 years ago 5 replies

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor? ...

What kind of problems have you experienced? How was there support? If you could do it again would you use the NIOS processor?


Please help me with the XR-16 design work

Started by Yi Zhang in FPGA-CPU21 years ago 1 reply

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the...

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the clock cycles of a specific C program). Those who also do the similiar work of multi-cpu (XR-16) design: please give me your kind advice and share some useful ex


Transputers [ was What are peoples opinion of the Altera Nios Processor? ]

Started by John Kent in FPGA-CPU21 years ago 5 replies

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate...

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate Virtex FPGA to play with. I'm using the BurchED FPGA board with the XC2S200. Are there any small 32 bit CPUs that will fit in a 200K gate FPGA ?


strange register behavior in Verilog blocks under Quartus II

Started by lionheart_99_de in FPGA-CPU19 years ago

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th


GNUPro Toolkit, crt0, Altera Nios confusion

Started by Nat Chan in FPGA-CPU20 years ago 1 reply

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that...

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that came with it. I keep getting errors that ld can't find crt0.o. So, I looked around the Nios documentation and couldn't find anything on c


ARM7 - FPGA

Started by sumana0281 in FPGA-CPU15 years ago 2 replies

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129...

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129 Arm processor with me. Does altera kit support for FPGA as well as ARM processor? or suggest any other option. kindly guide me. regards and thanx in advance sumana ------------------------------------ To post a message, send it to: f...@yahoogro...


Motorola 6805 core available for free

Started by jaquenodg in FPGA-CPU21 years ago 6 replies

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207...

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207 instructions, including MUL). Only 2 drawbacks: a) comments and an associated paper are written in Spanish. b) it's written using ALTERA AHDL, target


step by step cpu design using altera fpga

Started by SNFEDOGAN in FPGA-CPU13 years ago 14 replies

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent...

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent help is there any book, internet page, tutorial etc, which starts from scratch and goes up to design a simple cpu, including features such as, registers, in. sets, alu etc.... I am trying to prepare "Computer Architecture" class for computer e



The 2024 Embedded Online Conference