UARTs and FIFO

Started by extra300_it in LPC200012 years ago

Hello everybody. Has anybody used UARTS with FIFO enabled on LPC22xx? At first, I found this a big idea, but now that I'm trying to make...

Hello everybody. Has anybody used UARTS with FIFO enabled on LPC22xx? At first, I found this a big idea, but now that I'm trying to make it work it doesn't seem to be so good... The manual does not help much in explainig how they work. What about the FIFO reset bits? Do they work at all? What about the FIFO threshold settings? Apart from defa


LPC24xx ADC fifo

Started by "joris.mushrooms" in LPC20008 years ago 2 replies

Hey ! First, i'd like to thank everyone for their help on my previous posts! your advices were crucial for me. Today, i'm working around...

Hey ! First, i'd like to thank everyone for their help on my previous posts! your advices were crucial for me. Today, i'm working around adcs of lpc2478. I wonder if there are fifos on the adc. somewhere in the datasheet we can read, talking about adc "in non-fifo mode" but there is nothing about the fifo mode anywhere else. Can anybody confirm me there is no fifo? i also think the DMA i...


UART TX FIFO SIZE

Started by Hong Jiang in LPC200012 years ago 5 replies

Hi all members: I can get a Rx FIFO depth through FCR register,but how can I calculate the Tx FIFO size. According to the...

Hi all members: I can get a Rx FIFO depth through FCR register,but how can I calculate the Tx FIFO size. According to the LPC2119 document,this CPU's UART is compatible with the 16c550's which has a certain Tx FIFO size while I cann't find any words about that in philipse's documen


LPC2148, URAT and FIFO interrupts

Started by Jan Thogersen in LPC200011 years ago 1 reply

Hi all, I'm playing with the uart fifo's on the LPC2148 and I have some problems getting the receiver buffer timeout interrupt to work. When...

Hi all, I'm playing with the uart fifo's on the LPC2148 and I have some problems getting the receiver buffer timeout interrupt to work. When I disable the fifo the interrupt works just fine. I get the interrupt when the uart have received a new byte. However, when the fifo i on I should get an interrupt when the receiver times out. Maybe I haven't enabled the right interrupt... As far...


TX FIFO

Started by hodgejackiehank in LPC200013 years ago 24 replies

As soon as I write a single character to the THRE, Transmit holding register empty flag in U1LSR is cleared. Either the FIFO is not ...

As soon as I write a single character to the THRE, Transmit holding register empty flag in U1LSR is cleared. Either the FIFO is not enabled or is set to '1', or this is the normal operation (after all, the FIFO is not **empty**). In the latter case how do you know if there is


USART0's FIFO empty question

Started by naderus2000 in LPC200010 years ago 3 replies

I need to fill 16 byte each time i recieve INT.so i must sure the the FIFO is empty. For testing that the USART0's FIFO is fully empty is it...

I need to fill 16 byte each time i recieve INT.so i must sure the the FIFO is empty. For testing that the USART0's FIFO is fully empty is it enough to check the THRE or must test the TEMT?


LPC2129 A/D FIFO and accumulator

Started by Adam Wilkinson in LPC200012 years ago 1 reply

Hi Folks, Anyone know if there is a FIFO facility available for the A/D? Reference is made to it on p240 of the ...

Hi Folks, Anyone know if there is a FIFO facility available for the A/D? Reference is made to it on p240 of the LPC2119/2129/2194/2292/2294 User Manual, bit 30 of ADDR: In non-FIFO operation, this bit is cleared by reading this register. Is there an accumula


SSP FIFO

Started by medw...@... in LPC200012 years ago 1 reply

...of course when I say that the manual doesn't mention the size of the SSP FIFo I'm obviously ignoring the very first page describing the...

...of course when I say that the manual doesn't mention the size of the SSP FIFo I'm obviously ignoring the very first page describing the SSP Features where it says there is 8-frame FIFOs for both transmit and receive!!! Doh. Note to self, when searching manuals include FIFOs as well as FIFO in whole word searches.... ;-) Have I made a similar blunder in con


SD/MMC Interface (LPC2378) - reaction time in FIFO mode

Started by Mark in LPC20007 years ago 9 replies

Hi All Today I worked for the first time with the SD/MMC interface of the LPC23XX to read an SD card. Initially I did this using the FIFO but...

Hi All Today I worked for the first time with the SD/MMC interface of the LPC23XX to read an SD card. Initially I did this using the FIFO but am not sure whether this is a practical approach for real work. The reason is that the controller reads a complete block of data and the FIFO has space to hold maximum 16 x 4 = 64 bytes (I believe this is the case because the actual size doesn't seem t...


high performance UART FIFO usage

Started by naderus2000 in LPC200010 years ago 1 reply

I want to uart0 for tx long string with FIFO mode enable. what is the best performance wat to do that?I want the min time I must wait in this...

I want to uart0 for tx long string with FIFO mode enable. what is the best performance wat to do that?I want the min time I must wait in this function. here is a simple function for that: void UART0_String(char * str) { char i = 0; while(!(U0LSR &0x20));// see in FIFO is full free from last access while(*str != '\0') { U0THR = *str++; i++; ...


LPC2148 SSP FIFO manipulation

Started by deliconn in LPC200011 years ago

I am using the SSP on the LPC2148 as a buffered SPI interface to a custom CPLD design. I love the FIFO for transactions where I only need to...

I am using the SSP on the LPC2148 as a buffered SPI interface to a custom CPLD design. I love the FIFO for transactions where I only need to write to the CPLD. But when I need to read from it, I find that I need to do a full buffer flush with 8 read of SSPDR for before I execute my read. This seems like such a waste. Is there an easier way to flush the FIFO? Is there a way to have acc


Postpone interrupts on LPC21xx

Started by Jan Thogersen in LPC200011 years ago 1 reply

Hi all, I have a software fifo that is being filled up by my main loop and then grabbed by an interrupts routine (TMR0). When entering the...

Hi all, I have a software fifo that is being filled up by my main loop and then grabbed by an interrupts routine (TMR0). When entering the function that pushes a value onto the fifo I have to disable the TMR0 interrups to avoid that the interrupt routine breaks into the push algorithm and messes up the fifo pointer before the push algorithm is done. But by doing that I looses some TMR0...


Rx FIFO TRIGGER LEVEL(LPC2294)

Started by kooroshhajiani in LPC200010 years ago 3 replies

I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive interrupt. For example if I set it for 4 bytes(bits 7:6=01 in the FIFO...

I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive interrupt. For example if I set it for 4 bytes(bits 7:6=01 in the FIFO CONTROL REGISTER)and lets say that In my ISR, I move 4 bytes at a time(4 access to RBTR register) to a RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2 BYTES OF EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND FURTHERMORE...


REG: UART1 FIFO on LPC2104

Started by kumarvdpl in LPC200012 years ago 1 reply

Hi Friends, I am using lpc 2104. I am using IAR EMBEDDED WORKBENCH to develope program. I want to know about the Tx FIFO. I am writing...

Hi Friends, I am using lpc 2104. I am using IAR EMBEDDED WORKBENCH to develope program. I want to know about the Tx FIFO. I am writing values to UART1 TRANSMITTER HOLD REGISTER. I am not checking whether the U1THR is empty.The LPC 2104 has 16 bytes Tx FIFO.(as in data sheet). If i contineously writing the values to U1THR does it transmit the val


Setting uart FIFO level problem on LPC236x

Started by alin in LPC20007 years ago 4 replies

Hello, I'm having some difficulties in setting the uart FIFO level lower than 14 characters. Whatever i try to write in the FCR register, the...

Hello, I'm having some difficulties in setting the uart FIFO level lower than 14 characters. Whatever i try to write in the FCR register, the IIR register will always read 0xC1 (which means FIFO level 14) and my interrupt routine (triggered by RDA bit) will not trigger until i send 14 characters to the uart. The register gets set to this value regardless of what I actually write in it. This hap...


Write to MCI FIFO

Started by Kuba Dorzak in LPC20007 years ago

Hi, I'd like to write a value to the MCI's FIFO. To do this I: 1) switch on the MCI unit; PCONP |= PCONP_PCSDC; 2) set a...

Hi, I'd like to write a value to the MCI's FIFO. To do this I: 1) switch on the MCI unit; PCONP |= PCONP_PCSDC; 2) set a pointer on MCI's FIFO address; # define MCI_FIFO (MCI_BASE_ADDR + 0x80) unsigned char *dstAddr = (unsigned char *) MCI_FIFO *dstAddr = 0x55; However, dstAddr still contains 0x00. Is it possible to write a value the...


LPC213x UART1 RX/TX buffer

Started by jlowryspectrum in LPC200012 years ago 1 reply

Anyone know if I turn off the FIFO (U1FCR bit 0 = 0) will I still get interrupts (if enabled) when a single character is...

Anyone know if I turn off the FIFO (U1FCR bit 0 = 0) will I still get interrupts (if enabled) when a single character is received? Or does turning off the FIFO disable receiving and transmitting altogether? Thanks, Jeff.


LPC2138 TX FIFO full

Started by Lowry, Jeff in LPC200012 years ago 1 reply

If I enable the TX FIFO do I have to keep track of how many characters I've sent to THR so not to exceed 16? The transmit holding register ...

If I enable the TX FIFO do I have to keep track of how many characters I've sent to THR so not to exceed 16? The transmit holding register empty bit only says it's not empty. Any way of knowing it's full so I can stop sending chars?


SSP: How to clear transmit FIFO

Started by Gerhard Unrecht in LPC200012 years ago 8 replies

Hey, I want to clear the transmit-Fifo, to have a defined state. Knows anybody how to do do this? Regards Gerhard Unrecht ...

Hey, I want to clear the transmit-Fifo, to have a defined state. Knows anybody how to do do this? Regards Gerhard Unrecht


Software FLow Control With LPC UART

Started by suvidhk in LPC200011 years ago 13 replies

I am implementing software flow control and want to send an Xoff character.How can I Transmit a character without flushing the Transmit FIFO and...

I am implementing software flow control and want to send an Xoff character.How can I Transmit a character without flushing the Transmit FIFO and without waiting for Transmit FIFO to be empty (especiaaly suppose the remote UART has already sent a request to stop the transmission and the FIFO is holding data). Now I need to send a xonor xoff character without transmitting the data already in th...