EmbeddedRelated.com

LPC24xx ADC fifo

Started by "joris.mushrooms" in LPC200015 years ago 2 replies

Hey ! First, i'd like to thank everyone for their help on my previous posts! your advices were crucial for me. Today, i'm working around...

Hey ! First, i'd like to thank everyone for their help on my previous posts! your advices were crucial for me. Today, i'm working around adcs of lpc2478. I wonder if there are fifos on the adc. somewhere in the datasheet we can read, talking about adc "in non-fifo mode" but there is nothing about the fifo mode anywhere else. Can anybody confirm me there is no fifo? i also think the DMA i...


LPC2148, URAT and FIFO interrupts

Started by Jan Thogersen in LPC200018 years ago 1 reply

Hi all, I'm playing with the uart fifo's on the LPC2148 and I have some problems getting the receiver buffer timeout interrupt to work. When...

Hi all, I'm playing with the uart fifo's on the LPC2148 and I have some problems getting the receiver buffer timeout interrupt to work. When I disable the fifo the interrupt works just fine. I get the interrupt when the uart have received a new byte. However, when the fifo i on I should get an interrupt when the receiver times out. Maybe I haven't enabled the right interrupt... As far...


SD/MMC Interface (LPC2378) - reaction time in FIFO mode

Started by Mark in LPC200014 years ago 9 replies

Hi All Today I worked for the first time with the SD/MMC interface of the LPC23XX to read an SD card. Initially I did this using the FIFO but...

Hi All Today I worked for the first time with the SD/MMC interface of the LPC23XX to read an SD card. Initially I did this using the FIFO but am not sure whether this is a practical approach for real work. The reason is that the controller reads a complete block of data and the FIFO has space to hold maximum 16 x 4 = 64 bytes (I believe this is the case because the actual size doesn't seem t...


Rx FIFO TRIGGER LEVEL(LPC2294)

Started by kooroshhajiani in LPC200017 years ago 3 replies

I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive interrupt. For example if I set it for 4 bytes(bits 7:6=01 in the FIFO...

I'm having some issue with the FIFO TRIGGER LEVEL of the UART Receive interrupt. For example if I set it for 4 bytes(bits 7:6=01 in the FIFO CONTROL REGISTER)and lets say that In my ISR, I move 4 bytes at a time(4 access to RBTR register) to a RAM buffer, when I check the buffer I NOTICE THAT THE LAST 2 BYTES OF EVERY 4 BYTES IN THE CHARACTER STREAM ARE ALWAYS THE SAME AND FURTHERMORE...


SSP: How to clear transmit FIFO

Started by Gerhard Unrecht in LPC200019 years ago 8 replies

Hey, I want to clear the transmit-Fifo, to have a defined state. Knows anybody how to do do this? Regards Gerhard Unrecht ...

Hey, I want to clear the transmit-Fifo, to have a defined state. Knows anybody how to do do this? Regards Gerhard Unrecht


Software FLow Control With LPC UART

Started by suvidhk in LPC200017 years ago 13 replies

I am implementing software flow control and want to send an Xoff character.How can I Transmit a character without flushing the Transmit FIFO and...

I am implementing software flow control and want to send an Xoff character.How can I Transmit a character without flushing the Transmit FIFO and without waiting for Transmit FIFO to be empty (especiaaly suppose the remote UART has already sent a request to stop the transmission and the FIFO is holding data). Now I need to send a xonor xoff character without transmitting the data already in th...


Filling SSP fifo after GPDMA transfer

Started by Kuba Dorzak in LPC200012 years ago 1 reply

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to...

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to start transfer 5) when transfers from master and slave are finished I block at slave side GPDMA channels and reload fifo (using CPU) and wait for master to send next package. This way I expect to have valid data at master side- because I fill the fif...


DMA read from MCI fifo

Started by Kuba Dorzak in LPC200013 years ago 13 replies

Hi everybody, I am trying to use DMA transfer to get MCI fifo data. I used Juri Haberland's driver, which works perfectly with 1-bit SDbus...

Hi everybody, I am trying to use DMA transfer to get MCI fifo data. I used Juri Haberland's driver, which works perfectly with 1-bit SDbus without DMA. I can write data to MCI using the GPDMA, but reading fails. My question concerns DMA configuration: 1) firstly, I am setting DMA source, destination and channel 1 control: [code] else if (mode == dmaP2M) { ...


How Erase LPC2129-UART RX FIFO

Started by srk in LPC200017 years ago 1 reply

Hi The code written for rx data in LPC2129-uartO U0LCR = 0x83; U0DLL = 39; // baud rate = 9615 ...

Hi The code written for rx data in LPC2129-uartO U0LCR = 0x83; U0DLL = 39; // baud rate = 9615 @ pclk = 6mhz U0FCR = 0x07; //FIFO enable U0LCR = 0x03; //Rx data as 8 bits, no Parity, 1 Stop bit while(!(U0LSR & 0x01)); //executed untill U0RSR full while(U0LSR & 0x01) { ch3[x] = U0R...


LPC2119 How to block or disable interrupts momentarily

Started by "alastair.stell" in LPC200014 years ago 2 replies

Newbie unfortunately. I need to pass data received from a CANbus interrupt interrupt to the application (note I am not using an RTOS at...

Newbie unfortunately. I need to pass data received from a CANbus interrupt interrupt to the application (note I am not using an RTOS at present). I am looking for a safe way to pass data acquired by the interrupt into the application. I was hoping to use a simple fifo queue mechanism but I am concerned the application and interrupt might collide while accessing the fifo queue. So I was cons...


can't get uart tx fifo to work

Started by fhriley in LPC200013 years ago 12 replies

Hello, I've got my uart code working fine, however, when measuring it with a scope, it appears the TX fifo is not working. I send a byte with...

Hello, I've got my uart code working fine, however, when measuring it with a scope, it appears the TX fifo is not working. I send a byte with the following code: while ((LPC_UART-> LSR & LSR_THRE) == 0); LPC_UART-> THR = ch; I call this in a loop to send the message. I would expect this loop to be fast for the first 16 bytes, however I see the first byte take 830ns, the second 2.2us, and t


LPC214x: Can we really manage the SSP (SPI mode) in interrupt mode????

Started by croquettegnu in LPC200017 years ago 2 replies

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that...

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that allows to trig an interrupt as soon as the TX FIFO is half empty and the Rx FIFO is half full. These are the only flags that can be used to generate an interrupt (except error flags). But I do NOT understand how to manage my transfer with such inter...


LPC2478: SD card DMA

Started by John in LPC200013 years ago 9 replies

Hello! Sorry for my bad English! I need help. =) I write files on the SD card. I am using a filesystem from Keil. When I set the Base...

Hello! Sorry for my bad English! I need help. =) I write files on the SD card. I am using a filesystem from Keil. When I set the Base address of Cache Buffer in USB RAM - everything OK. But when I set the Base address in SDRAM (EMC) - its not work! I have a question - is the DMA of LPC2478 can to transmit data from the MCI FIFO to SDRAM? Or it can only transmit from the MCI FIFO to USB ...


UART TX FIFO and INTs problem

Started by forum_microbit in LPC200020 years ago 43 replies

Hi all, [I'm reposting on the URL, the new lpc2000 address doesn't seem to wor I'm a bit stuck with this one, and hope...

Hi all, [I'm reposting on the URL, the new lpc2000 address doesn't seem to wor I'm a bit stuck with this one, and hope someone has some advice, I must be overlooking something and I just don't see it....... I'm using Two 256 byte circular buffers for RX and TX In


uart tx overrun

Started by shwouchk in LPC200016 years ago 2 replies

Hi, I am writing code for handling uart right now, and I became concerned with the size of the Tx fifo and of overrunning it. I thought...

Hi, I am writing code for handling uart right now, and I became concerned with the size of the Tx fifo and of overrunning it. I thought about using the scratch register to count how many chars were sent and each time it gets to 16 to wait for a THRE interrupt to clear it. I think this method would be highly inefficient in terms of uart transmission rates. What would you recommend for ...


LPC2148 Uart Problem

Started by SUBRAMANIUM in LPC200013 years ago 1 reply

Hello am using LPC2148 controller. I have started to use WinArm complier now. Previously I was using Keil compiler. Now I am able to print data...

Hello am using LPC2148 controller. I have started to use WinArm complier now. Previously I was using Keil compiler. Now I am able to print data using both uart0 n uart1 but am not able to receive the data from either ports. my initialization routine is below. Kindly help. thanks in advance. /** * Initialize UART0, setup pin select, clock, parity, stop bits, FIFO, etc. * * @param baudrate...


Crossworks, C++, SPI, FIQ

Started by mjames_doveridge in LPC200016 years ago 6 replies

mornin' all.. A design change has left me with a requirement to use an SD card with the SPI interface on my LPC2129. This interface has no...

mornin' all.. A design change has left me with a requirement to use an SD card with the SPI interface on my LPC2129. This interface has no FIFO buffer and a high transfer rate, (well, can be, anyway). To implement the interface, I need to read/write 512-byte sectors. I have a couple of problems. All my comms IRQ interrupts have no nesting. I have only one buffer supply queue into all...


Questions on the UART Interface

Started by Leighton Rowe in LPC200019 years ago 12 replies

Just for clarification on the UART Block Diagram (see UM)... 1. Do U0TSR & U0RSR actually representthe Tx & Rx FIFO buffers? I ...

Just for clarification on the UART Block Diagram (see UM)... 1. Do U0TSR & U0RSR actually representthe Tx & Rx FIFO buffers? I only see U0TSR & U0RSR illustrated here and I can't find any other documentation for it. Now concerning U0THR & U0RBR (data r


LPC2468 & SC16IS752 DUART Anomaly

Started by KM Shore in LPC200015 years ago 2 replies

I am using both of these NXP parts with the DUART connected via one of the i2c busses to the 2468. After long periods of moderate traffic ...

I am using both of these NXP parts with the DUART connected via one of the i2c busses to the 2468. After long periods of moderate traffic (short bursts of 20 or fewer characters, followed by a few seconds of no traffic), the DUART will set an interrupt; the status(IIR) indicates that a stale character is in the receive FIFO. When the DUART is queried both the LSR and input character count (...


EFSL and SDHC

Started by drproton2003 in LPC200015 years ago 12 replies

Hello everyone, I am attempting to get EFSL to work with SDHC cards. I have downloaded version 0.2.9 RC7 from this page...

Hello everyone, I am attempting to get EFSL to work with SDHC cards. I have downloaded version 0.2.9 RC7 from this page http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/arm_memcards/ After realizing that I needed to use the SSP FIFO mode I had it working with a 1GB SD card. Now that I am using a SDHC card I am having some problems. The problems start in the sd_Init funct...