We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain...

We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain the test-bench written for the same. Yahoo! India Mobile: Ringtones, Wallpapers, Picture Messages and more.Download now.

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform...

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform Studio]. Since there are fixed possible sizes of BRAM which can be assigned,like for spartanIIe 2,4,8 KB First I tried executing with cache disabled-

Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one....

Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one. basically the microblaze document says that cache in microblaze is implemented using Block RAM and on the other hand he also says that Block RAM can

Dear, maybe interesting information for people who are new at softcore processors and busses. during the course of our...

Dear, maybe interesting information for people who are new at softcore processors and busses. during the course of our research project "embedded system design based on soft- and hardcore FPGA's", we've written: * a few reports : - about sev

Hello Group, I wanted to know the difference between these two books. Which is more helpful for a hardware student willing to...

Hello Group, I wanted to know the difference between these two books. Which is more helpful for a hardware student willing to build a small RISC? Computer Organization and Design: The Hardware/Software Interface by David A. Patterson, John L. Hennessy, Nitin Indurkhya

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that...

Hi, I'm trying to build some C code (separate .c files) and link the .o files together for Nios using the GNUPro tools that came with it. I keep getting errors that ld can't find crt0.o. So, I looked around the Nios documentation and couldn't find anything on c

For those following the Block RAM saga, the answer seems to be that I have my clock edges the wrong way round. I got RAMB4_S8...

For those following the Block RAM saga, the answer seems to be that I have my clock edges the wrong way round. I got RAMB4_S8 working as a ROM on my 6800 design by reversing the clock edges. I also managed to simulate block RAM by including the unisim library in the file

Hi, Im trying to interface a compact flash card to a Spartan2 FPGA in TrueIDE mode.I am having two main problems 1)My LBA...

Hi, Im trying to interface a compact flash card to a Spartan2 FPGA in TrueIDE mode.I am having two main problems 1)My LBA address is being ignored. If I write data to one address and read a different address, I still get the data back.Checking the Cylinder High\low registers

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600)...

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600) with ethernet+flash+ram+CPLD. please visit my site at http://snaplogix.tripod.com for more informat

** I am attempting to get information about the altera bitstream format ** I have already read ...

** I am attempting to get information about the altera bitstream format ** I have already read http://opencollector.org/news/Bitstream/ I wanted to make sure I wasn't missing something, is the information fo