VHDL tutorial - combining clocked and sequential logic

Gene Breniman March 3, 2008

In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a master clock rate of 40MHz. A reader of that article had written to ask if it was possible to extend the design to...

Designing Embedded Systems with FPGA-2

Pragnesh Patel November 13, 200710 comments

In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...

VHDL tutorial - part 2 - Testbench

Gene Breniman October 30, 20073 comments

In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE environment makes it pretty easy to start the testing process. To start the process, select "New Source" from the menu items under "Project". This launches the "New Source Wizard". From within the Wizard select "VHDL Test Bench" and enter the name of the new module (click 'Next' to...

Designing Embedded System with FPGA - 1

Pragnesh Patel October 28, 200711 comments

With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.


I will start with...

Handling Translations in an Embedded Project

Mattia Maldini October 13, 20234 comments

A brief walkthrough on how to handle human language translations in a low level C application. Some options are listed, each with advantages and disadvantages laid out.

nRF5 to nRF Connect SDK migration via DFU over BLE

Mike Voytovich September 7, 20232 comments

This writeup contains some notes on how I was able to migrate one of my clients projects based on the nRF5 SDK, to nRF Connect SDK (NCS) based firmware, via a DFU to devices in the field over BLE.

Getting Started With Zephyr: Saving Data To Files

Mohammed Billoo October 31, 2023

In this blog post, I show how to implement a Zephyr application to mount a microSD card, create a new file on the microSD card, and write data to it. The lessons learned from such an application can be helpful for devices out in the field that need to write data to off-board memory periodically, especially in cases where Internet access may be sporadic.

Getting Started With Zephyr: Writing Data to EEPROM

Mohammed Billoo December 6, 20235 comments

In this blog post, I show how to implement a Zephyr application to interact with EEPROM. I show how the Zephyr device driver model allows application writers to be free of the underlying implementation details. Unfortunately, the application didn't work as expected, and I'm still troubleshooting the cause.