Microblaze In FPGA Virtex4 ML401?

Started by mora...@yahoo.com in FPGA-CPU10 years ago 13 replies

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a...

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a microcontroller(ATMEGA8535) and the microcontroller is eventually connected to Xilinx Virtex4 (ML401).It is actually road traffic light implementation for Emergency Vehicle Preemption System. My friend told me that I could do this by implementing a Microbl...


Paul Metzgen on multiplexers and the NIOS II pipeline

Started by Tommy Thorn in FPGA-CPU10 years ago 5 replies

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen:...

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen: http://www.cs.tut.fi/soc/Metzgen04.pdf (I wish I had attended this talk). Among other things, he shows how on Stratix/Cyclone, a single LE can implement (assuming sclear and sload is shared between all LE in a LAB) if (sclear) q


Digilent's Nexys

Started by Manuel Toledo Quinones in FPGA-CPU11 years ago 7 replies

Hi, I want to introduce myself as new member of the list, and take advantage of the opportunity to ask a question about Digilent's...

Hi, I want to introduce myself as new member of the list, and take advantage of the opportunity to ask a question about Digilent's Nexys Spartan 3 board. I purchase the 1000k gate version. I would like to use the off-chip memory and tough that a good place to start was the build-in self test sources that the company provide in their web site. However, I get error when I try to re-synthesiz...


8-bit microprocessor

Started by ashfaq_bse in FPGA-CPU11 years ago 6 replies

hey people hop all of u ppl will b fine. i m a student of B.Sc. Computer engineering. i m going to make a degree project of "8-bit...

hey people hop all of u ppl will b fine. i m a student of B.Sc. Computer engineering. i m going to make a degree project of "8-bit microprocessor based on MIPS architecture (RISC) implemented on verilog and synthesized oin FPGA" if any one have this project he/she should help me out so that i could vast ma project scope. i shall b really grateful to u ppl. thanking u ppl in anticipa...


exclusive access RAM

Started by Rob Finch in FPGA-CPU11 years ago 5 replies

Have you ever looked at code guarded by mutexes and semaphores and wondered, "what if the guarded code were placed in a RAM block that ensured...

Have you ever looked at code guarded by mutexes and semaphores and wondered, "what if the guarded code were placed in a RAM block that ensured exclusive access to itself" ? Why not put the 'code' block in the 'RAM' block ? Then use a hardware guard, rather than using mutexes and semaphores. Faster and more efficient, although it does consume some more transistors.


Multi-context processor

Started by Rob Finch in FPGA-CPU11 years ago 16 replies

What's new with the new multi-context processor patent ? http://www.freepatentsonline.com/5872985.html To post a message, send it to:...

What's new with the new multi-context processor patent ? http://www.freepatentsonline.com/5872985.html To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


implementing memory mapped register

Started by windam_2000 in FPGA-CPU12 years ago 5 replies

Hi All, I'm new to fpga design and was trying to research on logic on how to implement several memory mapped registers on an FPGA. I'm trying...

Hi All, I'm new to fpga design and was trying to research on logic on how to implement several memory mapped registers on an FPGA. I'm trying not to take shortcuts by relying on the FPGA tool to make them for me, because I want to know how it's put together. I was thinking that it might consist of several decoders which generate signals that go the appropriate latches to store the data o


Re: Wishbone comments - SimpCon

Started by Martin Schoeberl in FPGA-CPU12 years ago 2 replies

Hi Kolja and all, > >> to get a draft of your spec. ... > The draft of the spec at the moment are few sketches on real > paper -...

Hi Kolja and all, > >> to get a draft of your spec. ... > The draft of the spec at the moment are few sketches on real > paper - takes some time to draw all diagrams for a document > (BTW does anybody know a tool for quick drawing of timing > diagrams). > The draft is still not written, but I've imp


Wishbone comments

Started by Martin Schoeberl in FPGA-CPU12 years ago 7 replies

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes...

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes it not the best choice for SoC interconnect. The Wishbone interface specification is still in the tradition of microcomputer or backplane busses. However, for a SoC interconnect, which is usually point-to-point, this is


System09 updates

Started by John Kent in FPGA-CPU12 years ago 4 replies

Just a notice to anyone playing with the System09 VHDL core, There are a few updates to the CPU09 core. JSR [0,S] did not work...

Just a notice to anyone playing with the System09 VHDL core, There are a few updates to the CPU09 core. JSR [0,S] did not work properly The stack pointer was pre-decremented ready to push the return address before the indexed effective address was calculated. EXG xx,CC and TFR xx,CC did not work properley. The ALU did not transfer


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