Hi all! I want to know the most optimal way to implement FIFO/LRU/Random in hardware. I am designing a cache and i need to implement...

Hi all! I want to know the most optimal way to implement FIFO/LRU/Random in hardware. I am designing a cache and i need to implement these as replacement algorithms. I guess this makes clear why i want a fast hardware solution for implementing these. regards, mnsharif

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. ...

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. HELP. Implementing CISC architecture processor in Book : Computer Designs Funtamentals, Morris Mano HELP

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me...

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilog thanks a lot

Can anyone think of a use for a two bit opcode ? It all started when I decided to use a 42 bit code. Three opcodes are packed into...

Can anyone think of a use for a two bit opcode ? It all started when I decided to use a 42 bit code. Three opcodes are packed into 128 bits, but that leaves 2 bits left over, so what can I do with them ?

Spotted this in comp.arch.transputer and in comp.arch.fpga by johnjakson JJ dated 02/04/2005 (yes 2nd of April) Announcement This...

Spotted this in comp.arch.transputer and in comp.arch.fpga by johnjakson JJ dated 02/04/2005 (yes 2nd of April) Announcement This first partial release date was chosen to be April 1st, to suggest some light hearted foolery here and to force myself to get something out to show for a couple years of work. Indeed the joke is really on all

See http://wiki.openchip.org/index.php/Cont est:SRL16. I've been waiting for some tiny bit-serial CPUs to emerge. This is your chance...

See http://wiki.openchip.org/index.php/Cont est:SRL16. I've been waiting for some tiny bit-serial CPUs to emerge. This is your chance at fame! (Well, what passes for fame on comp.arch.fpga.) :-) I think it would be most impressive if your CPU was C programmable and it could run a C simulation of itself.

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th

Dear all, Did anybody use the vga generator example for XS40 boards on www.xess.com before? Is that ready for use? I...

Dear all, Did anybody use the vga generator example for XS40 boards on www.xess.com before? Is that ready for use? I would like to read data from the SRAM and output the image on the VGA monitor. What should I do to the SRAM such that I can write data to it and

I just got off the phone with Digilent and apparently the 400K and 1000K Spartan 3 boards are availabel and shipping now. ...

I just got off the phone with Digilent and apparently the 400K and 1000K Spartan 3 boards are availabel and shipping now. Maybe $120 for 400K and $160 for 1000K It is supposed to be on the web site but I haven't seen it.

Mostly. This is neat http://news.com.com/Hobb yist+reconstructs+Apollos+computer/2100- 1003_3-5570963.html?tag=nefd.top...

Mostly. This is neat http://news.com.com/Hobb yist+reconstructs+Apollos+computer/2100- 1003_3-5570963.html?tag=nefd.top and so are some of the links from