I've been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount...

I've been looking at alternative chip packages to improve routing on tight boards. It seems like the issue is space for vias. Leaded surface mount parts have space under the chip body for vias. Most QFN devices do not, they have a thermal pad. A 16 pin TSSOP has a solder pad footprint of 5 mm x 7.3 mm, leaving a 5 mm x 4.3 mm space underneath for routing. I can fit a bunch of routin

Many times I'd like to replace libc functions in embedded systems, because of some tests or because I need a different implementation. For...

Many times I'd like to replace libc functions in embedded systems, because of some tests or because I need a different implementation. For example, sprintf implementation of newlib uses malloc and I can't use it many times. It sometimes happens that I can use malloc, with some restrictions. Just for test or optimization, I replace libc malloc with my own implementation. In these cas...

I design with a real-time, live "monitor" in my projects. It gives me low level access to everything happening in the device AS it is happening....

I design with a real-time, live "monitor" in my projects. It gives me low level access to everything happening in the device AS it is happening. I can attach to a particular process and examine/alter objects in its address space, pause/resume, stop/restart, etc. It's a poor-man's ICE with limited footprint (unlike supporting a full debugger in the release). For certain classes of projec...

You search for an affordable tool to design state diagrams and generate code from them? The SinelaboreRT focus is on generation of readable and...

You search for an affordable tool to design state diagrams and generate code from them? The SinelaboreRT focus is on generation of readable and maintainable code from hierarchical UML state machine diagrams - and activity diagrams. With its unique features the tool covers perfectly the requirements of embedded real-time and low-power application developers coding in C / C++. No comp

I'm just doing some rough prototyping at the minute and to save squinting I put a identifying label on the MCU showing part no and orientation,...

I'm just doing some rough prototyping at the minute and to save squinting I put a identifying label on the MCU showing part no and orientation, from one of those thermal Dymo-style labelling machines. What I hadn't anticipated is the bonus feature - these are thermal labels so of course give a visual indication when the magic smoke gets let out. http://andrews.freeshell.org/news/20220821.c...

ARM ABI says that the stack should be 8-byte aligned, but I see cases where the stack is aligned only to 4-byte boundary. For example, I have...

ARM ABI says that the stack should be 8-byte aligned, but I see cases where the stack is aligned only to 4-byte boundary. For example, I have the following simple busy-delay function: void delay(int iter) { int volatile counter = 0; while (counter < iter) { // delay loop ++counter; } } This compiles with IAR EWARM 9.10.2 on ARM Cortex-M to the following

I wonder why some developers choose non-free compilers (Keil, IAR, Cosmic, Raisonance, etc) when targeting architectures supported by the free...

I wonder why some developers choose non-free compilers (Keil, IAR, Cosmic, Raisonance, etc) when targeting architectures supported by the free Small Device C Compiler (SDCC). Answears that also mention the architecture besides the reasons would be particularly helpful.

In a given, nominal task (collection of related threads), how many "external interfaces" (hooks to/from other tasks) do you...

In a given, nominal task (collection of related threads), how many "external interfaces" (hooks to/from other tasks) do you typically have? Complexity is best managed when the number of such interactions is kept small and focused. But, what is a good target metric for this? [Clearly, each task needs to interact with at least one other task/driver to do meaningful work. But, at what poi...

I'm stuck with a stupid issue on a Cortex-M3 (LPC1788 by NXP). It's a classical issue that happens randomly and in different ways when the...

I'm stuck with a stupid issue on a Cortex-M3 (LPC1788 by NXP). It's a classical issue that happens randomly and in different ways when the code is slightly changed, so it's very difficult to debug. MCUXpresso (IDE from NXP) and Ozone (a software from Segger) says that IBUSERR and FORCED are set when HardFault exception occurs. I understand it is related to a program counter with a wron...

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go...

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of > 24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is required. This will give sub mHz resolution over the entire range. Nice for the low frequencies, but not of much use for MHz frequencies (in this application). Is there any objection to using a