pic18f452 interrupts

Started by vijayguru in comp.arch.embedded10 years ago 1 reply

how to handle 4 interrupts in pic18f452 out four interrupts 2 are low interrupts and other two are high but we are having only two vector address...

how to handle 4 interrupts in pic18f452 out four interrupts 2 are low interrupts and other two are high but we are having only two vector address plz suggest me anybody


enable/disable PCI interrupts

Started by Mark in comp.arch.embedded2 years ago 1 reply

As a course of learning linux device drivers, I'm implementing a PCIe driver, and I'd like to understand at what level the interrupts can be or...

As a course of learning linux device drivers, I'm implementing a PCIe driver, and I'd like to understand at what level the interrupts can be or should be enabled/disabled. I intentionally do not specify OS, as I'm assuming it should be relevant for any platform. By levels I mean the following: a) OS specific interrupts handling framework b) Interrupts can be disabled or enabled in th...


interrupts vs function calls

Started by kada...@gmai in comp.arch.embedded7 years ago 3 replies

I am new to embedded systems. I have few questions a)Can key board clicks be considered as hardware interrupts or software interrupts? b)...

I am new to embedded systems. I have few questions a)Can key board clicks be considered as hardware interrupts or software interrupts? b) How are interrupts different from function calls or subroutines? In both cases current state of execution is saved (in stack) and the Interrupt service routine or called function is executed and after finishing it, normal execution is resumed. ...


External Interrupts on an MPC555 with Quickstart Software

Started by mpcuser in comp.arch.embedded13 years ago 1 reply

Hello, I'm using the MPC500 quickstart libraries, but I'm having trouble using external interrupts. My board is a PB-0555 manufactured...

Hello, I'm using the MPC500 quickstart libraries, but I'm having trouble using external interrupts. My board is a PB-0555 manufactured by Axiom, and I'm using Codewarrior. I'm using the following code to initialize external interrupts: int init(void) { ioctl(USIU, USIUINT_INIT, NULL); /* enable external interrupts - i.e. set MSR[EE] and MSR[RI] bits */ archEnableInt(); ret...


Multiple UARTs and multiple interrupts

Started by Ross Marchant in comp.arch.embedded13 years ago 2 replies

Hi All I want some feedback as to whether what I am doing is correct. I am using a DS80C320 with a Phillips SC28L198 8 channel UART. ...

Hi All I want some feedback as to whether what I am doing is correct. I am using a DS80C320 with a Phillips SC28L198 8 channel UART. 2 interrupts are triggered by the internal UARTS, 1 by the phillips chip and another by timer 0. I have found that for reliable operation i must turn all interrupts off when servicing the internal uart interrupts, and when putting a character into the ring...


"signaling" interrupts in WinCE 5.0

Started by Roberto Waltman in comp.arch.embedded10 years ago

I am porting a touch-panel driver to a WinCE 5.0 device. It is interrupt driven, using the SYSINTER_TOUCH & SYSINTR_TOUCH_CHANGED...

I am porting a touch-panel driver to a WinCE 5.0 device. It is interrupt driven, using the SYSINTER_TOUCH & SYSINTR_TOUCH_CHANGED interrupts. To debug it, I need to simulate these interrupts from a timer thread, either on the driver itself or from an application. How do I do that? Somebody recommended to use events, but I do not see how to relate a user defined event to either one o...


Strange problem encountered with AVR and interrupts - 1 attachment

Started by Michael in comp.arch.embedded13 years ago 10 replies

Hi - I was attempting to get the two external interrupts working on an AVR. I have attached the code I wrote. My problem is that it seems it is...

Hi - I was attempting to get the two external interrupts working on an AVR. I have attached the code I wrote. My problem is that it seems it is only detecting when INT0 is pressed - but I'm not sure about this. The way I wrote it I never use the RETI statement - and I don't know if other interrupts can be called when a interrupt handler is running. But also - another problem - so to tr...


handling interrupts

Started by Radha_Purnima in comp.arch.embedded9 years ago 16 replies

how exactly are the interrupts get served in the real time embedded products like a washing machine,refrigirator? is it like, we will write a...

how exactly are the interrupts get served in the real time embedded products like a washing machine,refrigirator? is it like, we will write a program where we continuously check a particular status bit of the device has been set or not...or those interrupts will be hard wired to a interrupt pin (INT pin kind of)?? if it is hard wired how a variety of divices are connected to that particular ...


PCI FPGA Interrupt

Started by Ghostboy in comp.arch.embedded8 years ago

Hi, Below you find a part of the code of the PCI core. I can send a value from the computer to the FPGA and the LEDs on the development...

Hi, Below you find a part of the code of the PCI core. I can send a value from the computer to the FPGA and the LEDs on the development board will always change to the given value. The problem I have is that not all of the interrupts are detected by the computer. Sometimes it does, sometimes it doesn't. I look at the detected interrupts by Linux in /proc/interrupts. So if I enter 5 times...


Disabling interrupts to protect data

Started by KIRAN in comp.arch.embedded8 years ago 42 replies

Hi Guys, I am working on some RTOS, in which I see lot of interrupts "enabling" and "disabling" code in most of the RTOS API's to protect...

Hi Guys, I am working on some RTOS, in which I see lot of interrupts "enabling" and "disabling" code in most of the RTOS API's to protect kernel data. For example, Semaphore API's, Message Queue APIs, Runtime memory management API's. Is enabling / disabling interrupts only to protect the kernel data? Why I am asking this is whenever interrupts are disabled, I am scared of losing timer int...


Questions aboutreentrant interrupts on ARMv7

Started by Marek Omama in comp.arch.embedded6 years ago 6 replies

I am trying to figure out how reentrant interrupts are supposed to work on ARMv7. According to the ARM document DUI0203H, this is what you...

I am trying to figure out how reentrant interrupts are supposed to work on ARMv7. According to the ARM document DUI0203H, this is what you have to do: Example 6.16. Nested Interrupt (ARMv6, non-vectored interrupts) IRQ_Handler SUB lr, lr, #4 SRSFD #0x1f! ; Save LR_irq and SPSR_irq to System mode stack CPS #0x1f ; Switch to System mode ...


UARTs and interrupts

Started by Ross Marchant in comp.arch.embedded12 years ago 26 replies

Hi all, I have been writing code for the ds80c320 and xa-g49 and need a few questions answered that i'm unsure about. 1. Say i have timer 0...

Hi all, I have been writing code for the ds80c320 and xa-g49 and need a few questions answered that i'm unsure about. 1. Say i have timer 0 set to interrupt on overflow. If in another interrupt routine I disable all interrupts, then timer 0 happens to overflow, and then I enable all interrupts, while the timer 0 overflow isr then run, or was it missed? *** I use interrupt driven se...


Interrupts and Analog Devices ADuC842

Started by Walter Smits in comp.arch.embedded13 years ago 2 replies

Hi, We are experiencing some issues with external interrupts resetting an Analog Devices ADuC842 controller (8051 family). The system we are...

Hi, We are experiencing some issues with external interrupts resetting an Analog Devices ADuC842 controller (8051 family). The system we are working on analyses sensorial data from a rotary encoder connected to EX0. The interrupt is configured to be level-triggering. In our current set-up, the controller spontaneously resets when the rate with which the sensor interrupts occur exce...


Nesting interrupts in 8051

Started by Anonymous in comp.arch.embedded12 years ago 2 replies

If the 8051chip is servicing a lower priority interrupt and I want it to be interrupted by a higher priority interrupt, do I have to...

If the 8051chip is servicing a lower priority interrupt and I want it to be interrupted by a higher priority interrupt, do I have to enable interrupts - EA = 1 - as sson as I enter lower priority ISR. In other words, does the 8051 disables all interrupts when it enters an ISR ?


How to write an ISR in UCOS-ii

Started by Prakhar in comp.arch.embedded10 years ago 3 replies

Hello, I am developing a program which creates many tasks, schedules them and responds to external interrupts, when they ouccr. In my program...

Hello, I am developing a program which creates many tasks, schedules them and responds to external interrupts, when they ouccr. In my program in UCOS-ii, I have enabled the external interrupts (the values of the resgisters are set correspondingly). Now, I want to write the interrupts handler for this ext interrupt., i.e, an ISR. I tried the following ISR with an intention to write an ex...


Rising/Falling edge Interrupts and non-maskable interrupt

Started by galapogos in comp.arch.embedded11 years ago 1 reply

Hi, I'm working with an MCU that has 4 interrupts on external PINs, and I wish to interrupt on an active low input. However, 3 of the...

Hi, I'm working with an MCU that has 4 interrupts on external PINs, and I wish to interrupt on an active low input. However, 3 of the interrupts are active high interrupt while the last one, though it's an active low interrupt, is also labelled a non-maskable interrupt. I want to be able to mask the interrupt since I don't want it enabled all the time. Other than using an inverter, is there ...


Multiple Interrupt handling in XPS 8.2i

Started by moon in comp.arch.embedded8 years ago

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the...

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two interrupts.These interrupts pins are input to the interrupt controller INTC (1.00 c). Initially both interrupts are disabled.Then only high priority interrupt is enabled. What my objective is that when a high priority interrupt occurs:in its ISR it should dis...


Interrupts on Adlink PCO-7224 with PLX 9052?

Started by Thorsten Ostermann in comp.arch.embedded13 years ago 1 reply

Hi! I'm currently trying to use the onboard timer on the Adlink PCI7224 [1] to generate fast interrupts under WinNT/RTX. But I couldn't...

Hi! I'm currently trying to use the onboard timer on the Adlink PCI7224 [1] to generate fast interrupts under WinNT/RTX. But I couldn't manage it to generate an interrupt. The interrupthandler is attached and reacts on software triggered interrupts. But also the timer i8254 is running, no "local" interrupt at the PLX 9052 is generated, and so #INTA line does not change. I also trie...


The idea of disabling interrupts

Started by karthikbalaguru in comp.arch.embedded10 years ago 23 replies

Hi, Is it a good idea to disable interrupts while sharing data (Critical Sections) ? Thx in advans, Karthik Balaguru

Hi, Is it a good idea to disable interrupts while sharing data (Critical Sections) ? Thx in advans, Karthik Balaguru


TC1796 disable/enable interrupts

Started by beartech in comp.arch.embedded5 years ago

Hello, using TC1796 microprocessor, can't disable and enable interrupt around critical sections of code. Any suggestions? Referring to the...

Hello, using TC1796 microprocessor, can't disable and enable interrupt around critical sections of code. Any suggestions? Referring to the Tricore Architecture Volume 1 manual: The processor is running in User-1. In this mode you should be able to disable and enable interrupts. checked in debugger, PSW.IO = 0x01, User-1 Mode, "Tasks at this level may disable interrupts." (quoting the above ...