Virtual memory and memory protection

Started by ssubbarayan in comp.arch.embedded12 years ago 58 replies

Dear all, I went through one good tutorial on virtual memory in this...

Dear all, I went through one good tutorial on virtual memory in this website: http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Memory/virtual.html The article says that virtual memory can help in protecting memory of the applications process.That means each individual process running in the CPUs memory can be protected. I am not able to realise how this could help in protection?AFAIK...


MicroBlaze program memory vs data memory

Started by Anonymous in comp.arch.embedded2 years ago 2 replies

Hi everyone, I am currently writing a linker script to build my final executable to fit into the memory space visible from within the MB. Since...

Hi everyone, I am currently writing a linker script to build my final executable to fit into the memory space visible from within the MB. Since that CPU is an Harvard architecture based, program memory and data memory are separated. This means that I have instructions at address 0 of the program memory, and a data at the same address but in data memory. If I try to force the .data


writing program memory programmatically in MB-lite

Started by alb in comp.arch.embedded3 years ago 9 replies

Hi there, I'm trying to understand if in an MB-lite I could use the program to read/write itself. The main idea behind is the...

Hi there, I'm trying to understand if in an MB-lite I could use the program to read/write itself. The main idea behind is the implementation of a 'memory scrubber' which detects and corrects errors in its own instruction memory (thanks to an EDAC). I know that Hardware Architecture has program memory and data memory separated and I believe that instruction memory can only be fetch...


allocate 10 GB of memory dynamically

Started by karthikbg in comp.arch.embedded11 years ago 14 replies

Hi, I have 1 GB RAM (Physical Memory) and 90 GB Harddisk (Logical Memory). Is it possible to allocate 5 GB of memory dynamically. But...

Hi, I have 1 GB RAM (Physical Memory) and 90 GB Harddisk (Logical Memory). Is it possible to allocate 5 GB of memory dynamically. But Dynamic memory allocation depends on Heap that we have. I believe that heap cannot be allocated to have around 8 GB of memory. (But, some tricks must be there to have around 8 GBs of Heap :) :) !! ) Kindly tell some tricks for assigning big amount (...


how to implement multi-port memory in FPGA?

Started by Pasacco in comp.arch.embedded11 years ago 1 reply

hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some...

hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some logic should wrap the memory, but i do not have idea how to implement. Does anyone point me to where i can find document or material or literature ? Thankyou


data memory mapping microblaze

Started by alb in comp.arch.embedded2 years ago 1 reply

Hi everyone, I'm dealing with an mb-lite which is clone of the microblaze architecture and I'm trying to understand how the memory mapping...

Hi everyone, I'm dealing with an mb-lite which is clone of the microblaze architecture and I'm trying to understand how the memory mapping works. We have memory mapped registers which are needed to exchange data between the uP and the FPGA and it should be pretty straight forward to map this memory into a segment in 'data memory', but unfortunately it seems the object-dump does not s...


Debugging Embedded Dram - Need Help

Started by Jim Flanagan in comp.arch.embedded9 years ago 3 replies

Hi - I'm attempting to debug a problem with an existing embedded controller board. The board uses a MC68020 and uses either 1 or 2 banks of...

Hi - I'm attempting to debug a problem with an existing embedded controller board. The board uses a MC68020 and uses either 1 or 2 banks of 30pin simm memory. I think this is a 199? design. The board supports either 1M or 4M memory. The SIMM memory is configured to be accessed as a 16bit wide data bus. The 1M memory works OK, but there are read/write errors when using the 4M memory...


virtual memory

Started by khan in comp.arch.embedded11 years ago 17 replies

I want to clear my virtual memory concept. Is virtual memory, a part of hard disk or NAND Flash (some indirect addressable memory).

I want to clear my virtual memory concept. Is virtual memory, a part of hard disk or NAND Flash (some indirect addressable memory).


side effects problem.

Started by leilei in comp.arch.embedded9 years ago 10 replies

Hi, I am reading , In section 9.1.1, it described the side effect about memory access: The main difference between I/O registers and RAM is...

Hi, I am reading , In section 9.1.1, it described the side effect about memory access: The main difference between I/O registers and RAM is that I/O operations have side effects, while memory operations have none: the only effect of a memory write is storing a value to a location, and a memory read returns the last value written there. Because memory access


Looking for free memory pool software

Started by Baron Samedi in comp.arch.embedded10 years ago 6 replies

I don't want to reinvent the wheel, so I am looking for some freely reusable memory pool software. Something tried, tested and efficient. - It...

I don't want to reinvent the wheel, so I am looking for some freely reusable memory pool software. Something tried, tested and efficient. - It should dynamically allocate memory from a statically allocated structure or structures, for use in an embedded system. - it should be coded in C++ (or C). - it should allow user defined handling of the "out of memory" situation. - garbage col...


Mixing 12 nS memory with 15 nS memory

Started by D. Zimmerman in comp.arch.embedded13 years ago 4 replies

I have a Zilog development system (the Acclaim) and I need to add some SRAM. I'm running into a lot of problems finding 3 pcs. of 12...

I have a Zilog development system (the Acclaim) and I need to add some SRAM. I'm running into a lot of problems finding 3 pcs. of 12 nS, 512K x 8 memory, so I would like to know if anyone has had problems mixing 12 nS with 15 nS SRAM. It looks like 15 nS memory should work because there is an added cycle (20 nS) anyway, but I'm hesitant to go forward unless I know that t...


Memory selection for an embedded system

Started by Anonymous in comp.arch.embedded11 years ago 6 replies

Hi all, I'm currenlty gettting into embedded system architecture and would like to know where can I find any kind of tutorial/articles/lecture...

Hi all, I'm currenlty gettting into embedded system architecture and would like to know where can I find any kind of tutorial/articles/lecture notes regarding the "art" of selecting the memory for my design I.E. what kind of memory to use SDRAM , SRAM ,FLASH ,EEPROM and where to use it. another thing I'm looking for is stuff on the subject of memory mapping I.E. how to arrange the different ...


Memory Mapped Vs I/O Mapped Vs others

Started by karthikbg in comp.arch.embedded11 years ago 26 replies

Hi, What is the actual difference between the following : "Memory Mapped" Vs " I/O Mapped" Vs "Memory Mapped I/O" Vs " I/O Mapped...

Hi, What is the actual difference between the following : "Memory Mapped" Vs " I/O Mapped" Vs "Memory Mapped I/O" Vs " I/O Mapped Memory" ? Kindly tell me their actual definitions/meanings . Further, Let me know some best conditions whereit should be used and other scenarios where it should not be used. Need some clarifications / links / docs. Thx in advans, Karthik Balagur...


Memory Suggestions

Started by Gromer in comp.arch.embedded12 years ago 2 replies

Hi, I have one basic doubt on how MEMORY WR/RD# cycles are emulated.. (i.e memory read & write cycles emulated in software).. How is the...

Hi, I have one basic doubt on how MEMORY WR/RD# cycles are emulated.. (i.e memory read & write cycles emulated in software).. How is the Assertion/Deassertion of WR/RD pins taken care (emulated) in software whenever a memory address is being deferenced. Thanks


Detailed memory usage by module on a PIC18

Started by Nickolai Leschov in comp.arch.embedded9 years ago 8 replies

Hello, I have a legacy project for PIC18F452 that compiles with HI-TECH Software C Compiler, using MPLAB IDE. The device's flash program...

Hello, I have a legacy project for PIC18F452 that compiles with HI-TECH Software C Compiler, using MPLAB IDE. The device's flash program memory is nearly full and I'm curious to see what occupies most of this space. How can I see memory footprint of compiled program, by modules? The project consists of 19 'C' files; if the compiler told me how much memory each one uses, that would be...


Testing Flash Memory Question

Started by panfilero in comp.arch.embedded9 years ago 11 replies

I am purchasing a Nand-Flash memory chip.... just stand alone only flash... not a microcontroller or anything. I was wondering if anyone knew...

I am purchasing a Nand-Flash memory chip.... just stand alone only flash... not a microcontroller or anything. I was wondering if anyone knew of any interfaces or test boards (maybe they are called flash controllers? I'm not sure) that I could use to test the memory... basically I will write a little code to read and write, and then check that the memory is ok. So far I have found this: ht...


Confused about large/small memory models for C281x

Started by Chris Carlen in comp.arch.embedded13 years ago 4 replies

Hi: I am beginning work with the TMS320F2812 on the eZdsp platform. Most of the examples are done with the -ml compiler option. Since the...

Hi: I am beginning work with the TMS320F2812 on the eZdsp platform. Most of the examples are done with the -ml compiler option. Since the memory is "unified" meaning that program and data memory are in the same address space even if read by different busses, what is the point of using the large model IF one has no need to read/write data from program memory? (Note I will be using C...


Xbox2 has less graphics-memory bandwidth than Playstation2 ????

Started by MS Will Destroy Sony Computer Entertainment in comp.arch.embedded12 years ago 1 reply

this is an attempt to make a comparison between the graphics memory bandwidth of the now old Playstation2 which was developed in the...

this is an attempt to make a comparison between the graphics memory bandwidth of the now old Playstation2 which was developed in the mid-to-late 1990s, and the forthcoming Xbox2 which has been developed over the last 3 or so years, thus, obviously is much newer than the Playstation2. It is a comparison of the bandwidth of the embedded memory / on-chip memory / memory that is built into t...


Regarding calculation of free memory

Started by ssubbarayan in comp.arch.embedded12 years ago 62 replies

Gurus, I was just wondering what could be the best possible way to calculate free memory while our code is running in SDRAM.I have used vxworks...

Gurus, I was just wondering what could be the best possible way to calculate free memory while our code is running in SDRAM.I have used vxworks and it uses a approach to calculate the free memory as follows: Fill up the entire stack with 0xeeeee and then when you start using the stack,if at all a particular address in memory is used,the value of 0xeeeee in that location should be overwritten...


Boot Block and Uniform Block Flash Memory and Executin In Place(XIP)

Started by karthikbalaguru in comp.arch.embedded10 years ago 17 replies

Hi, I understand that boot block Flash Memory have "protected boot blocks" so they can not be erased accidentally unless special functions...

Hi, I understand that boot block Flash Memory have "protected boot blocks" so they can not be erased accidentally unless special functions are used to do that. Further, Top Boot Block Flash memory are intended for microprocessors that begin execution by reading from the top of their memory space. And vice versa for Bottom Boot Bloc Flash Memory. Here, the Boot Block is positioned at th...