What is the cause of a "can not see clock" problem in logic analyser?

Started by Acceed See in comp.arch.embedded13 years ago 3 replies

My LA is agilent 16702. When I use the 400MHz internal clock to sample the clock pin and the data pin with probes, I can see them nicely on the...

My LA is agilent 16702. When I use the 400MHz internal clock to sample the clock pin and the data pin with probes, I can see them nicely on the LA, and positive edge of the clock is right in the middle of the data. When I change to sampling data with my external clock pin, LA told me the clock is too weak and can not see a clock in the top-right banner. Of course, I don't see any data. W...


what's shift clock

Started by leilei in comp.arch.embedded9 years ago 6 replies

hi, when i read rtl8139 driver's source, there's a macro like this: #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ the comment say it is a...

hi, when i read rtl8139 driver's source, there's a macro like this: #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ the comment say it is a eeprom shift clock. can any one tell me what is shift clock.and what it is used to do?


Ration between MCU and JTAG/SWD clock (Cortex-M and others)?

Started by Uwe Bonnes in comp.arch.embedded2 years ago 12 replies

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but...

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but facts for other archs are welcome. Information floating aound in the net tells abound a factor of 6, but some people tell about successfull SWD communication even with a MCU clock much slower than the SWD clock. Thanks -- Uwe Bonnes ...


clock cycle calculations

Started by faz in comp.arch.embedded10 years ago 1 reply

Hi all, I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms. I am confused to...

Hi all, I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms. I am confused to calculate the cycles for memory and IO related instructions... For example MOV AL,33H ------> Took 3 clk cycles for my design OUT 32H,AL------> Fetching and decoding takes ----10 clock cycles write in to memory starts after three clock cycles of fetc


Clock cycles

Started by arshadnatasha in comp.arch.embedded9 months ago 6 replies

Hi all: I have been stuck on this problem for a while - can someone help me figure this out? For the following instruction, the instruction set...

Hi all: I have been stuck on this problem for a while - can someone help me figure this out? For the following instruction, the instruction set manual says it should take 5 clock cycles, whereas according to my measurements using an oscilloscope, I should get 4 clock cycles. What could be the reason for the difference? I am using TelosB. add #1, -4(r4) -------------------------------...


alarm clock

Started by polder_udo in comp.arch.embedded12 years ago 2 replies

hello i'm a quite newby to embedded systems and have some basic questions to you. i'd like to build up a alarm clock which has some special...

hello i'm a quite newby to embedded systems and have some basic questions to you. i'd like to build up a alarm clock which has some special features as: - radio controlled - LED projection on wall/ceiling - fully customizeable awake times (this is the main reason), eg. mo, fri, 14.4.2007 ..... of course the clock needs to have a display with backlight (on keypress) sounds like a ...


Clock Divider in a 22V10

Started by sam in comp.arch.embedded13 years ago 17 replies

Hello all: I have a 6.144Mhz crystal and I am trying to generate the 9600*16 ~ 154k clock needed by the 8251 UART and the ~ 1Mhz system...

Hello all: I have a 6.144Mhz crystal and I am trying to generate the 9600*16 ~ 154k clock needed by the 8251 UART and the ~ 1Mhz system clock. I dont want to use the 74ls* series ripple counters and I have a bunch of 22v10 PAL chips lying around. I have been thinking about how best to do this, using what I have. Basically I need to divide the 6.144Mhz by 40. First by 5 to real...


turn your expensive oscilloscope into a $5 clock

Started by BrunoG in comp.arch.embedded10 years ago 45 replies

Hi, Here is my suggestion to turn your oscilloscope into a clock with a PIC a 4 resistors...

Hi, Here is my suggestion to turn your oscilloscope into a clock with a PIC a 4 resistors : http://www.micro-examples.com/public/microex-navig/doc/082-pic-oscillo-clock I'm opened to your destructive comments :) Bruno


SPI & I2C....NOT GETTING CLOCK OUTPUT

Started by abhay in comp.arch.embedded11 years ago 10 replies

hi, i am trying with SPI code provided for LPC2138 provided on philips site.but its strange that i am not able to observe the clock output...

hi, i am trying with SPI code provided for LPC2138 provided on philips site.but its strange that i am not able to observe the clock output on CRO. i have tried with a resistor connected in series with clock output before connecting on CRO probe.also i have provided high to the SSEL pin of LPC2138 to configure to as master. now i m observing clock output on its SPICLK pin with common ground. ...


dsPIC PWM phase noise

Started by Thomas Magma in comp.arch.embedded8 years ago 3 replies

I'm trying to figure out if I can run the dsPIC33 at the maximum 40MIPS and use the PWM output to clock an external ADC without introducing the...

I'm trying to figure out if I can run the dsPIC33 at the maximum 40MIPS and use the PWM output to clock an external ADC without introducing the phase noise(into the ADC) associated with the internal clock PLL. Is there a way to have the dsPIC processor use the clock PLL but have the PWM circuitry directly referenced to the external clock? Thomas


PIC 18 Reset Problem

Started by Tim Wescott in comp.arch.embedded10 years ago 19 replies

I have an odd little problem, I'm hoping one of you could shed some light on it before I spend hours tracking it down. I'm working on a board...

I have an odd little problem, I'm hoping one of you could shed some light on it before I spend hours tracking it down. I'm working on a board with a PIC18F8722. We're setting it up to work in external clock mode with a 40MHz clock. This clock is, in turn, sourced by an integrated oscillator module from ECS (ECS-8FM). The problem that we're seeing is that sometimes the thing comes up ...


Modification of Linux driver atmel_serial.c to use it in synchronous mode with external clock?

Started by wzab in comp.arch.embedded6 years ago 1 reply

Hi, I need to use the USART in AT91SAM9260 working under Linux OS (quite old 2.6.29.3 version, due to compatibility with some parts of...

Hi, I need to use the USART in AT91SAM9260 working under Linux OS (quite old 2.6.29.3 version, due to compatibility with some parts of the system) to communicate with peripheral sending data in synchronous mode with clock 6MHz. The peripheral provides clock. The standard atmel_serial.c driver does not seem to support operation with external clock neither the synchronous mode. (In fact it...


Implementing Real Time Clock in the ATmega128

Started by mkoswatte in comp.arch.embedded8 years ago 9 replies

Hello I am new to Atmel I am trying to make a data collecting device and send data over GPRS but problem is I need to integrate real time clock...

Hello I am new to Atmel I am trying to make a data collecting device and send data over GPRS but problem is I need to integrate real time clock calender in the device to gather information when the data is collected? There are two options 1.Use Atmega128 timer/clock 2.Use separate chip with clock calender But i need to have separate battery powered system to keep the time up to date so...


atmega48 adc at faster than best clock speeds

Started by Hul Tytus in comp.arch.embedded8 years ago 2 replies

comp.arch.embedded atmega48 adc at faster than best clock speeds Atmel's atmega48 manual states the adc clock should run between 100 kcs &...

comp.arch.embedded atmega48 adc at faster than best clock speeds Atmel's atmega48 manual states the adc clock should run between 100 kcs & 200 kcs for best, most accurate conversions. They also state that higher clock rates can be used, presumably when a higher sampling rate is to greater advantage than best accuracy. Has anyone checked the accuracy of these converters when used with ...


Virtex-5 clocking

Started by Saul Bernstein in comp.arch.embedded9 years ago 4 replies

Hi Folks, altough brand new I hope someone already made some experience with Virtex-5. I just switched from Virtex-4 to Virtex-5 and I...

Hi Folks, altough brand new I hope someone already made some experience with Virtex-5. I just switched from Virtex-4 to Virtex-5 and I must admit that the clock managment is... and remains... somewhat unclear to me! It's plain to see that the clock management is handled a bit differently than Virtex-4. Virtex-5 clocking uses both DCM (digital clock managers) technology for delay ...


vhdl code

Started by jebei.jabai in comp.arch.embedded9 years ago 2 replies

I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be...

I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be divided first in order to can create PWM with 40 kHz frequency and 0.75 duty cycle.Can someone send me a VHDL CODE for a clock divider. Please show by example, I'm new to logic design. Thanks, jebei


Update on MSP430 Babylonian clock

Started by larwe in comp.arch.embedded10 years ago 2 replies

Followup to the message I posted the other week about Nokia 2260 LCDs for my Babylonian clock... the electronics are now working. The clock...

Followup to the message I posted the other week about Nokia 2260 LCDs for my Babylonian clock... the electronics are now working. The clock starts at 10:12:10 and ends at 10:13:08 in this video; you get to see most of the digits. It was slightly tricky to fit the 59 digits (at 32 x 22 pixels) into the 2K MSP430; I wound up making a set of sub-


multiple clock domain

Started by dargo in comp.arch.embedded9 years ago 5 replies

Hello, I have a design with 2 clocks provied to my FPGA (Spartan 3-A). The first one comes from an external oscillator @ 50MHZ. The second...

Hello, I have a design with 2 clocks provied to my FPGA (Spartan 3-A). The first one comes from an external oscillator @ 50MHZ. The second one also comes from an external BUS clock (75MHZ). The 75MHZ is the main system clock. It is used to feed an internal AMBA bus. The 50MHZ is needed to compute with precision a frame (customer need) with a very low BER. How can I synchronize those ...


External clock in cypress EZ-USB FX2

Started by sanika in comp.arch.embedded8 years ago 4 replies

hello, I am working on a cypress chip. I want the communication between endpoints and host to work on external clock. Is it possible for chip to...

hello, I am working on a cypress chip. I want the communication between endpoints and host to work on external clock. Is it possible for chip to work on external clock without being in Slave FIFO or GPIF mode? Regards Sanika


How to distribute a clock source?

Started by amerdsp in comp.arch.embedded10 years ago 3 replies

If you have more than one (3 or 4) component that you want to run on the same clock. What clock source is used in this case and what is the...

If you have more than one (3 or 4) component that you want to run on the same clock. What clock source is used in this case and what is the best way to distribute it? Thank you, A