Is all SRAM created equal?

Started by Jim in comp.arch.embedded13 years ago 9 replies

For our prototypes we used STMicroelectronics SRAM 4Mbit, 512Kx8, 55ns (M68AW511AL). Now it is getting near production I find that they have...

For our prototypes we used STMicroelectronics SRAM 4Mbit, 512Kx8, 55ns (M68AW511AL). Now it is getting near production I find that they have stopped making that memory. Lots of other companies make equivalent SRAM, but can I assume it is going to work ok? Our application requires an access time of 60ns to the SRAM, so within the SRAM spec. In an ideal world I'd get one of the new types a...


Replacing PCMCIA SRAM card?

Started by Arash Salarian in comp.arch.embedded13 years ago 2 replies

Hi, I'm working with an old design that uses PCMCIA SRAM cards to store data. Today these cards are very expensive so I wonder if I can...

Hi, I'm working with an old design that uses PCMCIA SRAM cards to store data. Today these cards are very expensive so I wonder if I can replace the SRAM card with a Flash card. I was thinking of using a Linear Flash card but I've never used such a thing before. I don't know how different they are from SRAM. SRAM card was simply a memory space in my microcontroller's view so there was reall...


Problem with writing values to SRAM from XMD

Started by Roman in comp.arch.embedded10 years ago 2 replies

Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I...

Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I want to write and read from SRAM, it is only possible if there is instruction and data cache enebled and I add XCache_EnableCache in the beginning of the code. So far it works. Then I tried to run application from SRAM. So I generated linker script tel...


LPC1768 copy & execute isr from sram

Started by navman in comp.arch.embedded6 years ago 2 replies

Hi, Is there any example code to make the ISR to run out of SRAM. I know that it involves the following steps: 1) Copy ISR from flash to...

Hi, Is there any example code to make the ISR to run out of SRAM. I know that it involves the following steps: 1) Copy ISR from flash to SRAM. 2) Copy vector table to SRAM 3) Remap vector table to SRAM using VTOR I'm struggling here. Any examples for such code? I'm using the LPC1768 processor with LPCxpresso IDE/compiler. I need to do this to avoid the annoying lag when jumping to interrup...


Urgent Help required Regardind File system for SRAM

Started by Naveen in comp.arch.embedded11 years ago 7 replies

Hi All, I am having a 512K SRAM which is used for storing some specific data. The OS runs on a 64MB flash and SRAM is external to this. The OS...

Hi All, I am having a 512K SRAM which is used for storing some specific data. The OS runs on a 64MB flash and SRAM is external to this. The OS used is WinCE 4.2. I want to have some kind of filesysytem for SRAM for storing my data from application running over the OS. Is there any commerical File system available matching my requirememts?? I am ready to purchase it..Kinldy reply..


AT91 - Execution out of internal SRAM

Started by Dan Rhodes in comp.arch.embedded13 years ago 3 replies

Hi All - I'm trying to set up my code to execute out of internal SRAM on an AT91FR40162 using the IAR EWARM toolset. Does anyone have any...

Hi All - I'm trying to set up my code to execute out of internal SRAM on an AT91FR40162 using the IAR EWARM toolset. Does anyone have any advice on how to do this? If the linker thinks ROM starts at 0x00000000 (which it does prior to remap) and the remap command moves the internal SRAM to address 0x00000000, there should be no problem simply copying the code from flash into sram before...


"Executing code in SRAM" with AVR

Started by jamie in comp.arch.embedded10 years ago 9 replies

Hello I have a question about "executing code in SRAM" with Atmega128 MCU. I know instructions (code) in flash rom area can be executed by...

Hello I have a question about "executing code in SRAM" with Atmega128 MCU. I know instructions (code) in flash rom area can be executed by AVR cpu and now I'm wondering if the code in SRAM can also be executed. Imagine I have some AVR instructions ( or function code ) in SRAM area, If I jump program counter to the area ( in SRAM ) then will the instruction be executed without any proble...


Interfacing AT91SAM9260 with cheap SRAM or SRAM?

Started by Mark in comp.arch.embedded11 years ago 2 replies

I was hoping to only spend $1 to $2 for 32k SRAM (or SDRAM) to interface with the AT91SAM9260. Looking at the schematic for the AT91SAM9260...

I was hoping to only spend $1 to $2 for 32k SRAM (or SDRAM) to interface with the AT91SAM9260. Looking at the schematic for the AT91SAM9260 evaluation board, I can see it uses two Micron MT48LC16M16A2 32KB SDRAM chips. Looking on digikey.com and avnet.com, this chip is about $7 in quantities of 10,000, which is much too expensive for the project. Does anyone think I will be able to find 32...


state of PIC SRAM on boot

Started by kyle york in comp.arch.embedded10 years ago 9 replies

Greetings, What is the state of the PIC SRAM on power up? Random value, determined value, last set value? Long ago I thought I'd read that...

Greetings, What is the state of the PIC SRAM on power up? Random value, determined value, last set value? Long ago I thought I'd read that unlike DRAM, SRAM maintains its values on power down, but I cannot find a reference to that at the moment. -- Kyle A. York Sr. Subordinate Grunt


____SRAM_gets__cleared use CS2 to power

Started by werty in comp.arch.embedded11 years ago

SRAM has 2 ChipSel lines , modern CPU with battery backup has a std method of safeing SRAM , using this 2nd ChipSelect pin ... ...

SRAM has 2 ChipSel lines , modern CPU with battery backup has a std method of safeing SRAM , using this 2nd ChipSelect pin ... "CS2" -------- SRAM has 2 sizes , small is CMOS , 5 microamps stdby Big is DRAM , 70Microamps stdby but they call it PSRAM . ______________________________________________________- Thx for the info. But, Gel file comes into picture, onl...


8051 64K external SRAM possible?

Started by andrew queisser in comp.arch.embedded13 years ago 4 replies

I'm planning to add some external SRAM to my 8051. I've seen many examples how to add 32K but never 64K. Is it possible to have the full...

I'm planning to add some external SRAM to my 8051. I've seen many examples how to add 32K but never 64K. Is it possible to have the full external data space in SRAM? If so, do I just hardwire the CE line to always select the chip? Thanks, Andrew


Speed problems with ARM7, more detailed post..

Started by webwraith067 in comp.arch.embedded13 years ago 17 replies

I have built a fully functional ARM7 prototype board based on the Atmel AT91R40008 processor. Everything works fine, but the performance...

I have built a fully functional ARM7 prototype board based on the Atmel AT91R40008 processor. Everything works fine, but the performance of the processor is approximately 1/10th what it should be. In a simple in SRAM memory write test, I first copy my code to SRAM, and then run out of SRAM and write blocks of 32 bytes to consequetive locations in an unrolled loop for a total of 9600 byte...


ASYNC SRAM selection

Started by Neven Colak in comp.arch.embedded13 years ago 1 reply

Hi, Does anyone know if 4ns ASYNC SRAM is available? I am designing a system which connects to a 64-bit TS202 tigersharc DSP at a...

Hi, Does anyone know if 4ns ASYNC SRAM is available? I am designing a system which connects to a 64-bit TS202 tigersharc DSP at a system clock of 100MHz and in order to get a zero-wait state system I need 4ns ASYNC SRAM.. perferably in a 64-bit package (but highly unlikely)... I'd be happy to find a 16 bit device and just populate 4 of them. Any help is appreciated. Neven


Reset should not clear SRAM

Started by karthikbg in comp.arch.embedded11 years ago 5 replies

Hi, My SRAM ranges from 20000000 to 2003E7FF (250Kbytes) in OMAP 5912 .I have some data stored in it by my application, so that it can be...

Hi, My SRAM ranges from 20000000 to 2003E7FF (250Kbytes) in OMAP 5912 .I have some data stored in it by my application, so that it can be used by my application when it gets loaded after reset . But, When i reset my OMAP 5912 processor by configuring the ARM_RSTCT1 to 0x08,(Global reset ) i find that SRAM gets cleared. But, 0x08 actually implies Reseting of DSP, MPU and Peripherals only...


sram vs sdram

Started by Anonymous in comp.arch.embedded10 years ago 8 replies

seems a lot of applications use sdram rather then sram. What are the pros and cons of each? The only siginifacnt difference I see is density.

seems a lot of applications use sdram rather then sram. What are the pros and cons of each? The only siginifacnt difference I see is density.


AVR studio Watch window giving unbelievable result.

Started by Denis Gleeson in comp.arch.embedded13 years ago 6 replies

Hello all Im new to using Atmel devices and AVR studio. We have built a project with avr-gcc and Im using AVR studio version 4.08 to debug....

Hello all Im new to using Atmel devices and AVR studio. We have built a project with avr-gcc and Im using AVR studio version 4.08 to debug. the device is the ATMEGA162. My problem is that we have an array of structures declared in C and when I place a watch in the watch window the SRAM address is given as 0x051E which is outside the SRAM space of the device which has 1k of SRAM starti...


Sram pins normalized?

Started by pes in comp.arch.embedded12 years ago 4 replies

Hi, I don' t understand why two SRAM of 64k Words in my case have not got the same address pins order, although it is not important in my...

Hi, I don' t understand why two SRAM of 64k Words in my case have not got the same address pins order, although it is not important in my case. There is not a standard? Thanks.


SRAM source?

Started by David Huseby in comp.arch.embedded13 years ago 2 replies

I'm putting together a new design with an MC68HC000FN16 at the heart of it. I want to use Hitachi HM658512L SRAM's but I've been unable to find...

I'm putting together a new design with an MC68HC000FN16 at the heart of it. I want to use Hitachi HM658512L SRAM's but I've been unable to find a retailer for the chip online. Anybody know of a source for those chips? I'd also like to add in the SGS-Thomson MK68901 multi-function paripheral to my design but I'm not sure anybody sells those anymore. Any help would be appreciated. Thanks. ...


Strategy to recover from checksum errors?

Started by Juergen Marquardt in comp.arch.embedded13 years ago 5 replies

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a)...

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a) battery buffered static ram (SRAM, 128 kByte) and b) battery buffered static ram (so called CMOS ram in clock chip, some 10 bytes) and c) Compact Flash card (some MByte) It is relatively easy to find out a sram area having been currupted by calculating ...


SRAM with multiplexed bus

Started by Meindert Sprang in comp.arch.embedded13 years ago 17 replies

Hi all, Many mainstream microcontrollers have an external multiplexed memory bus. They all require a latch to connect an SRAM chip. One would...

Hi all, Many mainstream microcontrollers have an external multiplexed memory bus. They all require a latch to connect an SRAM chip. One would expect there would be a manufacturer who sells SRAMs in 8k or 32kbyte size with a bus that connects glueless to these micro's but I cannot find such a device. Do they exist? Meindert