C-to-Verilog for embedded designs

Started by Nadav Rotem in comp.arch.embedded9 years ago

Hello, My name is Nadav and I operate the website http://www.c-to-verilog.com ; In the website people can cut-and-paste their C code and it...

Hello, My name is Nadav and I operate the website http://www.c-to-verilog.com ; In the website people can cut-and-paste their C code and it will "compile" and synthesize it into a Verilog module. You can later synthesize the core to an FPGA and connect it to a SoC design. The generated Verilog is optimized for size, frequency and cycles. The trade-offs can be decided by the user. I try to...


Verilog Simulator

Started by ngsa...@gmail.com in comp.arch.embedded11 years ago

Hi, all I recently developed a Verilog Simulator for Windows-platform. It's called LogicSim and is free for the time being. It supports most...

Hi, all I recently developed a Verilog Simulator for Windows-platform. It's called LogicSim and is free for the time being. It supports most of the Verilog-2001 constructs, and has a very good Verilog text editor and development environment. I'm currently in the process of adding a waveform editor, mixed-languages (VHDL, SystemVerilog, etc.), VPI/PLI and Linux support. I'd be glad if you ...


Verilog modeling.

Started by Artem in comp.arch.embedded13 years ago 1 reply

Hi all. I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a Quartus II. How I can use this model in this software? I have...

Hi all. I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a Quartus II. How I can use this model in this software? I have read in manual that verilog simulation is not supported by quartus.


Converting C-style include file to Verilog?

Started by Frank Miles in comp.arch.embedded13 years ago 4 replies

I have a system that includes both C (for a microprocessor) and Verilog code. Where these components interact, I would like to have a...

I have a system that includes both C (for a microprocessor) and Verilog code. Where these components interact, I would like to have a single source file from which certain relevant constants are derived. Initially, at least, I'm looking for a way to simply generate a Verilog file from a 'C' include file. This would be pretty straightforward except for the macros in C. (I wrote one but it...


VHDL/Verilog Book Recomendations?

Started by PagCal in comp.arch.embedded12 years ago 1 reply

What would be the best starter book for learning both VHDL and Verilog? As well, the book should talk about design techniques of CPLD's and...

What would be the best starter book for learning both VHDL and Verilog? As well, the book should talk about design techniques of CPLD's and FPGA's.


Icarus Verilog for Windows

Started by Pablo Bleyer Kocik in comp.arch.embedded13 years ago 3 replies

Hello people. I will be maintaining recent snapshots of the Icarus Verilog compiler for the Windows platform in easy to use installers...

Hello people. I will be maintaining recent snapshots of the Icarus Verilog compiler for the Windows platform in easy to use installers at http://armoid.com/icarus/. I have been doing this for more than a year now for the people in my company so I thought, what the heck, for the same effort I can benefit other users out there. If you have other free related goodies that can be posted th...


ANNC: Verilog Coding for FPGA Webcast

Started by bart in comp.arch.embedded10 years ago

Lattice is holding a webcast tomorrow, Wednesday, April 9, "Optimizing Verilog Coding for More Efficient FPGA Synthesis." The presenter will be...

Lattice is holding a webcast tomorrow, Wednesday, April 9, "Optimizing Verilog Coding for More Efficient FPGA Synthesis." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, starting a few hours after the liv...


VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract

Started by Specialist Verilog Engineers Roles in comp.arch.embedded10 years ago 3 replies

My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with...

My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with strong Verilog VHDL experience then we would like to hear from you. C++ and FPGA experience would be a nice to have. If you want to be part of an unrivalled technical broadcast engineering team then please call us. We have 15 Long Term Contract roles ...


I2C master connected and tested with LEON Processor

Started by Pinhas in comp.arch.embedded10 years ago

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order...

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also contains a test bench and simulation model for slave, written in VERILOG. From the VERILOG test...


RTL for Z8000 series CPU?

Started by ajcrm125 in comp.arch.embedded12 years ago 41 replies

Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam ajcrm125@gmail.com

Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam ajcrm125@gmail.com


Test Driven Development (TDD) Framework for Embedded Systems

Started by Anonymous in comp.arch.embedded3 years ago 11 replies

Hi, We currently do most (all) our embedeed FW testing on either real HW (if available), using FPGA, or using HW simulator and Verilog...

Hi, We currently do most (all) our embedeed FW testing on either real HW (if available), using FPGA, or using HW simulator and Verilog models. We are looking at performing more testing on the "Host" rather than the target, and since this is new to our group, I am looking for suggestions and comments. BTW, we use C, currently we don't use an RTOS, but going forward, this is something that we wil...


What graphical entry/documentation tools?

Started by jamesp in comp.arch.embedded12 years ago 2 replies

Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the...

Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy. Is there anything out there that will allow me to represent my design in some sort of hierarchical functional blocks to us...


FIFO hdl code

Started by Anonymous in comp.arch.embedded12 years ago 4 replies

Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the...

Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the different clock boundaries. I was wondering if anyone had some startup verilog code on FIFOs, I am using a Xilinx FPGA Thanks Ryan (ryan.pinto79@gmail.com)


Configuring sccb for OV9650 cmos camera

Started by maximili in comp.arch.embedded8 years ago 3 replies

Hi all. I have just purchased the omnivision 9650 cmos camera for my project of image processing and i wish to interface the camera with...

Hi all. I have just purchased the omnivision 9650 cmos camera for my project of image processing and i wish to interface the camera with the Altera DE2 FPGA board. For this I need to write the configuration in verilog code program but I do not have a clue about how to write it. Can anyone here provide any guidance? Thanks a lot. --------------------------------------- This messa...


best way to simulate multi core architecture ?

Started by TheWhizKid in comp.arch.embedded12 years ago 6 replies

Hi guys, Please give me some suggestions ! 1. I need to make a cycle accurate simulator for a dual core cpu. How do I pass external events...

Hi guys, Please give me some suggestions ! 1. I need to make a cycle accurate simulator for a dual core cpu. How do I pass external events like interrupts from one core to another during the simulation ? 2. How does one make a "C" reference model talk to a verilog model during a simulation ? is "PLI" the only way ? Thanks thewhizkid


powerPC simulation

Started by san in comp.arch.embedded11 years ago 1 reply

Hello, am New to PCB board design cycle. Working on circuit having powerPC interfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do...

Hello, am New to PCB board design cycle. Working on circuit having powerPC interfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do the cycle accurate Functional simulation of the above circuit. How should i go for it? Queries: 1. Which tool i should use. 2. Do i need to convert schematics into verilog? 3. Do i need Models for all the components in the circuit. What is the p...


audio fingerprinting using fpga

Started by vibz86 in comp.arch.embedded8 years ago

Hi, I have to implement audio fingerprinting in fpga using verilog. As Im new to fpga, Im finding it hard to start with this. Can someone send me...

Hi, I have to implement audio fingerprinting in fpga using verilog. As Im new to fpga, Im finding it hard to start with this. Can someone send me any sample codes of audio fingerprinting or any usefull links that will help me to learn and do this project quickly --------------------------------------- This message was sent using the comp.arch.embedded web interface on http://www.E...


Software to generate jed file for PAL chips

Started by CFF in comp.arch.embedded14 years ago 7 replies

Hi, I need to program a couple of old small assorted brand PAL (including GAL) chips. Is there any free software tool that can generate...

Hi, I need to program a couple of old small assorted brand PAL (including GAL) chips. Is there any free software tool that can generate jed files from Verilog (or ABEL and schematic) entry so that I can export to a universal programmer for downloading purpose? Thanks for any help. CFF


Processor Selection for SoC

Started by moogyd in comp.arch.embedded8 years ago 10 replies

Hi, I am looking at selecting a processor for our SoC platform. Currently we use an embedded 8051 core (small, low power, low...

Hi, I am looking at selecting a processor for our SoC platform. Currently we use an embedded 8051 core (small, low power, low performance, cheap). For our next project, we need more performance, and we are also trying to create a platform suitable for all future projects. The CPU must be available as RTL (VHDL or Verilog) source. Obviously, there are lots of options - Faster 8051 ...


Does UART is inbuild in FPGA

Started by leenaselvam in comp.arch.embedded10 years ago 3 replies

Is there UART in FPGA or whether UART has to be connnect externally..and how can we send information from FPGA through UART to...

Is there UART in FPGA or whether UART has to be connnect externally..and how can we send information from FPGA through UART to Ethernet........can anyone give guidence for writing coding either in VHDL or in Verilog for sending information from FPGA to Ethernet through UART