Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

Started by Kutaj Vamor in comp.arch.embedded12 years ago 4 replies

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and...

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and better by experimenting. What would you recommend for beginners like me to getting started with VHDL and FPGA experimentation ? Which SW (for WinXP and/or Fedora Linux ) for VHDL? Which start-up experimentation board for FPGA? Which URL, books etc ...


VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)

Started by Anonymous in comp.arch.embedded13 years ago 14 replies

I'm new to VHDL and I want to learn as with examples. I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie A,B...

I'm new to VHDL and I want to learn as with examples. I want to build a 16,24 or 32 bit counter for quadrature encoder signals (ie A,B signals). Can someone help me how to create following functionality in VHDL ? Inputs are (1,2) A, B = A,B quadrature signals (from encoder) ( 3) IDX = Index (from encoder) ( 4) RST = Reset (Low-> Reset counter) ( 5) S/P = Serial/


VHDL/Verilog Book Recomendations?

Started by PagCal in comp.arch.embedded12 years ago 1 reply

What would be the best starter book for learning both VHDL and Verilog? As well, the book should talk about design techniques of CPLD's and...

What would be the best starter book for learning both VHDL and Verilog? As well, the book should talk about design techniques of CPLD's and FPGA's.


Basic VHDL Development kit

Started by Tom Lucas in comp.arch.embedded10 years ago 21 replies

Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much more than toggle a few...

Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much more than toggle a few output pins and I'm happy to make up my own programming leads etc. UK based distributors would be preferred.


ATMEL support / Are they serious ?

Started by Fred Bartoli in comp.arch.embedded13 years ago 6 replies

Hello, I've designed in an instrument board an ATMEL CPLD. For that purpose I had to use their "low cost" software. First I tried the CUPL...

Hello, I've designed in an instrument board an ATMEL CPLD. For that purpose I had to use their "low cost" software. First I tried the CUPL tool, but it was too much bugged. Then I used their VHDL "prochip designer" which is based on altium tool and their proprietary fitters. After some fighting with VHDL (my first project) I finally had it all OK with simulation, synthesis and fitting (PA...


vhdl code

Started by jebei.jabai in comp.arch.embedded8 years ago 2 replies

I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be...

I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be divided first in order to can create PWM with 40 kHz frequency and 0.75 duty cycle.Can someone send me a VHDL CODE for a clock divider. Please show by example, I'm new to logic design. Thanks, jebei


Problems with VHDL lookup table in Quartus

Started by Rhydian in comp.arch.embedded7 years ago 2 replies

[Also posted to comp.lang.vhdl by mistake, sorry about that] Hi, I'm trying to debug a Cyclone design which writes values taken from...

[Also posted to comp.lang.vhdl by mistake, sorry about that] Hi, I'm trying to debug a Cyclone design which writes values taken from a lookup table to the address inputs of a crosspoint analog switch. The problem is that everything looks OK in the Quartus simulator, but when I test the design on the target hardware it seems to be pulling the wrong values out of the LUT. I have tried en...


interfacing a xilinx FPGA with a coldfire processor

Started by dargo in comp.arch.embedded9 years ago 1 reply

Hi, I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL interface with an external COLDFIRE processor. Due to...

Hi, I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL interface with an external COLDFIRE processor. Due to hardware considerations (not mine) I need to use 9 bits of address and 16 bits of datas, The following signals are available on my incoming pinout : TA, TEA, CS1, IRQ1 and R/W. Has anybody a clue where I can get some VHDL/Verilog code to help me? Thanks in adv...


2D array of std_logic_vector in VHDL

Started by westocl in comp.arch.embedded8 years ago 1 reply

Hello all. I am new to VHDL and I was looking for help crating a 2D array of std_logic_vectors and initilizing it. i think i got the first...

Hello all. I am new to VHDL and I was looking for help crating a 2D array of std_logic_vectors and initilizing it. i think i got the first part correct, as there were no errors compiling and syntesizing in ISE. my sytax is type ARR is array (1 downto 0, 1 downto 0) of std_logic_vector(3 downto 0); signal my_array : ARR; now i wanted to initilize the data i used my_array(0,0) ...


Simulating Microblaze Core + C Code + VHDL defined peripherical

Started by Xabier Iturbe in comp.arch.embedded11 years ago

Iam designing a system consisting of: Microblaze Core RS232 Uart Lite SPI controller The SPI controller will communicate with an ADC...

Iam designing a system consisting of: Microblaze Core RS232 Uart Lite SPI controller The SPI controller will communicate with an ADC converter placed outside of FPGA. In order to modelize the system, previous to implement it, I have included an VHDL model of the converter. I don=B4t know what is the best way to simulate the system whole.. ModelSim is a harware simulator and I think t...


Cheapest FPGA board to study VHDL on

Started by samiam in comp.arch.embedded11 years ago 26 replies

Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) Whats the cheapest board to study VHDL on? Ideally Id like an FPGA...

Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) Whats the cheapest board to study VHDL on? Ideally Id like an FPGA based board with a few inputs (dip switches,toggles?), some outputs (parallel or serial connector, some leds) < $100 I am looking on ebay now, and I see one or two boards well above $100. Any suggestions? Thanks in advance


VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract

Started by Specialist Verilog Engineers Roles in comp.arch.embedded10 years ago 3 replies

My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with...

My client is an award winning leader in their global field, and looking to expand their broadcast engineering team. If you are an engineer with strong Verilog VHDL experience then we would like to hear from you. C++ and FPGA experience would be a nice to have. If you want to be part of an unrivalled technical broadcast engineering team then please call us. We have 15 Long Term Contract roles ...


MIL-STD -1553 bus protocol design help

Started by pshabnavees in comp.arch.embedded11 years ago 1 reply

hi i am doing a project on MIL-STd-1553B. my project is to design and implement the mil-std-1553B bus protocol using VHDL. i could...

hi i am doing a project on MIL-STd-1553B. my project is to design and implement the mil-std-1553B bus protocol using VHDL. i could gather only info regarding the protocol concepts but not any design helping topics in VHDL. i would be thankful if someone can help me in guiding me or suggesting me the way to approach the design part.


I2C master connected and tested with LEON Processor

Started by Pinhas in comp.arch.embedded10 years ago

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order...

This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested. The core also contains a test bench and simulation model for slave, written in VERILOG. From the VERILOG test...


Using Spartan 3e

Started by Manish in comp.arch.embedded11 years ago 2 replies

Hi everyone, Does any one has used Sparan 3e with ise 8.02i??Please help me to learn VHDL.If you have any tutorial then post

Hi everyone, Does any one has used Sparan 3e with ise 8.02i??Please help me to learn VHDL.If you have any tutorial then post


RTL for Z8000 series CPU?

Started by ajcrm125 in comp.arch.embedded12 years ago 41 replies

Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam ajcrm125@gmail.com

Hey guys, does anyone know where I can get VHDL/Verilog source for the Z8001/Z8002 processor? Thanks for any info! -Adam ajcrm125@gmail.com


using C/C++ with microblaze

Started by jeanronald in comp.arch.embedded10 years ago 1 reply

I don't understand the link between my hdl ip and the C code, How can I access a port declared using vhdl using c code.

I don't understand the link between my hdl ip and the C code, How can I access a port declared using vhdl using c code.


JTAG implementation

Started by Giovanni in comp.arch.embedded13 years ago 1 reply

Hello everybody. I'm interested in developing a JTAG system using a FPGA programmed in VHDL. Is there some good source on line that can help me...

Hello everybody. I'm interested in developing a JTAG system using a FPGA programmed in VHDL. Is there some good source on line that can help me in doing that? Where can I found the specification of JTAG standard? Are they free available?


32 bit convolution with vhdl

Started by vickey_18 in comp.arch.embedded9 years ago 2 replies

Hello All I am currently working on a design in which I have to perform a 32 bit convolution. Can anyone give any ideas of doing this with...

Hello All I am currently working on a design in which I have to perform a 32 bit convolution. Can anyone give any ideas of doing this with maximum parallel processing so device utilization is minimum?? Thank You.


about vhdl compiling

Started by ravikumardk in comp.arch.embedded8 years ago 7 replies

while i compile any program in window 98 it shows that "error: can't open nhdl work " can somebody help on this and how to fix this...

while i compile any program in window 98 it shows that "error: can't open nhdl work " can somebody help on this and how to fix this problem. The same program compiles successfully in window xp or vista but in 98 it doesn't.