ChipHit ASIC, FPGA, EDA Search Engine

Started by ted in comp.arch.embedded10 years ago

Hi, I debated putting this announcement here, however, if you are doing ASIC, or FPGA embedded design, this might be of help. I recently...

Hi, I debated putting this announcement here, however, if you are doing ASIC, or FPGA embedded design, this might be of help. I recently created a Google custom search engine called ChipHit at http://www.chiphit.com. Please take a look and provide suggestions. I spend many hours a day searching the internet for ASIC, FPGA, and EDA tool topics as I am ASIC/FPGA applications engineer. F...


Debugging by bsing SW interrupts instead of HW interrupts

Started by Anonymous in comp.arch.embedded12 years ago 4 replies

My problem is to test my driver software ,but the asic chip is not ready yet.I can simulate the registers of the asic easyly,but the HW...

My problem is to test my driver software ,but the asic chip is not ready yet.I can simulate the registers of the asic easyly,but the HW interrupts which will be generated by asic chip is necessary to test my interrupt handler and interrupt driven SW. For X86 processor I know that also SW interrupt generation is possible but how? How should I write interrupt handler for a SW interrupt? Does...


Nucleus Porting to ASIC based on ARM926EJ-S

Started by bhaskar in comp.arch.embedded11 years ago 3 replies

Dear All, I have plans to work on ASIC based on ARM926EJ-S core. I am planning to port the Nucleus RTOS to the ASIC. I find the ARM core is...

Dear All, I have plans to work on ASIC based on ARM926EJ-S core. I am planning to port the Nucleus RTOS to the ASIC. I find the ARM core is well supported in the Nucleus RTOS. How to analyze the porting requirements to a supported processor but for different set of peripherals? I have downloaded the NucleusSIM from the site. Can this be useful to me understanding the HAL layer along...


ASIC development question

Started by Keith Brafford in comp.arch.embedded13 years ago 6 replies

Hey folks, I am working on a project where our cost and size are creeping up and some of our management are starting to ask about whether or...

Hey folks, I am working on a project where our cost and size are creeping up and some of our management are starting to ask about whether or not we need to be considering going to ASIC technology. Fortunately, our budget allows us to consider this option. Since I have never been in charge of a project that designed its own chip, I have a few Q's that I hope the embedded folks can ...


Tech: Help Identifing a Motorola ASIC / FPGA

Started by Jim Knight in comp.arch.embedded12 years ago 1 reply

Looking to identify an "ASIC" and find information on same. Known info is as follows: Motorola 84pin PLCC Circa Mid-late 1980's 2 MHz...

Looking to identify an "ASIC" and find information on same. Known info is as follows: Motorola 84pin PLCC Circa Mid-late 1980's 2 MHz clock rate (in one application) Marking line1 - M (Duh!) Marking line2 - S38FC049PIO3 Marking line 3 - ZKZKAC9039 Speculative information: This module was programmed locally. Any guesses? I can post a picture if it would...


Compatible data flash for AT45DB321D

Started by prabash in comp.arch.embedded7 years ago 3 replies

Hi, I did a design with AT45DB321D to use with ASIC. the ASIC development kit contained the AT45DB321D 32Mbit flash and I use the same thing in...

Hi, I did a design with AT45DB321D to use with ASIC. the ASIC development kit contained the AT45DB321D 32Mbit flash and I use the same thing in my design. But now unfortunately the AT45DB321D 32Mbit chip is out of stock every where and it has 7 months lead time. is there any one who know a compatible part for this serial flash --------------------------------------- Posted t...


AES encrytion (ASIC)

Started by Anonymous in comp.arch.embedded9 years ago 2 replies

Hey folks , i need ur opinion about something : To implement an AES decryption (CBC mode ) algorithm in ASIC , what would be the best way to do...

Hey folks , i need ur opinion about something : To implement an AES decryption (CBC mode ) algorithm in ASIC , what would be the best way to do it ? i mean among these architectures which one do you choose and why : * Basic iterative architecture * Partial loop unrolling * full loop unrolling * Partia outer-round pipelining * Full outerround pipelining * Inner-round pipelining * Part...


What's the maximum RAM size that can be embedded in an ASIC today?

Started by Anonymous in comp.arch.embedded4 years ago 21 replies

Hi all, Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? In general, what would be the maximum I could...

Hi all, Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? In general, what would be the maximum I could fit, if cost is not a limitation? Why? Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each. Or another possible partition (again...


How much RAM can I embed inside an ASIC design today?

Started by juangui in comp.arch.embedded3 years ago 5 replies

Hello all, Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? In general, what would be the maximum I...

Hello all, Is it possible to embed 10 or 100 or 1,000 GBytes of RAM inside an ASIC design today? In general, what would be the maximum I could fit, if cost is not a limitation? Why? Our need would be for a large number, but could be split into many independent banks if that makes things easier. For example, 1,000 independent banks of 100 MBytes each. Or another possible partition (ag...


suggestions for good MPEG encoder dev kit, embedded hard disk dev kit

Started by wallge in comp.arch.embedded10 years ago 5 replies

Does anyone know if there is a dev kit available for an MPEG encoder ASIC - preferably one that I could connect to a real-time video source as...

Does anyone know if there is a dev kit available for an MPEG encoder ASIC - preferably one that I could connect to a real-time video source as input and connect to an FPGA board for post processing... In otherwords an MPEG ASIC dev kit with a lot of IO options. Also can anyone suggest a (separate, additional) dev kit that would support reading and riding to a hard disk, preferably one that...


Why D flip flop is widely used in ASIC?

Started by Ajab in comp.arch.embedded9 years ago 6 replies

There must be some reason....Can anybody post it here?

There must be some reason....Can anybody post it here?


can anyone explain some terms?

Started by Anonymous in comp.arch.embedded11 years ago 5 replies

Application Specific Standard Product(ASSP) Structured ASIC configurable processor I am not a IC design,but a embedded software...

Application Specific Standard Product(ASSP) Structured ASIC configurable processor I am not a IC design,but a embedded software engineer. A few new terms come to me and I have no idea. I can find plenty of information on the internet, but none of them explains the terms. So can anyone give me an introductionary explanation and give one example each? thanx


Development tools comments

Started by Anonymous in comp.arch.embedded9 years ago 1 reply

Hi Experts, Let me start by providing some background. We have designed an ASIC: 8051 + non standard peripherals (timers etc) + FLASH + RF...

Hi Experts, Let me start by providing some background. We have designed an ASIC: 8051 + non standard peripherals (timers etc) + FLASH + RF frontent for a product used in wireless communications. The 8051 currently has a single breakpoint register, and we have managed to integrate with the Keil debugger (single stepping and breakpoints seem to work OK) Anyway, we are now looking at t...


Router/packet classifier hardware design

Started by vbalasu in comp.arch.embedded7 years ago 1 reply

I am investigating possible hardware implementation of a router/packet classifier in ASIC/FPGA. Where can I find the relevant information to...

I am investigating possible hardware implementation of a router/packet classifier in ASIC/FPGA. Where can I find the relevant information to start with. --------------------------------------- Posted through http://www.EmbeddedRelated.com


VGA controller

Started by damir in comp.arch.embedded12 years ago 4 replies

I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC...

I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC (LCD controller) or FPGA (VHDL core) design will do. Thanks, Damir


Schematic Edition Tool : Suggestions

Started by Francisco Camarero in comp.arch.embedded13 years ago 15 replies

Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on...

Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on teaching VHDL during the past years with very good results from our students. However, we have the impression that these students have difficulties working with schematics as tools to document and express their architectural ideas, in part because we di...


newbie: FIFOs in C for DSP

Started by sebastian in comp.arch.embedded13 years ago 7 replies

hi, im a newbie in DSP and embedded programming and i've some doubts that i hope some of you could kindly answer. i've to do some profiling...

hi, im a newbie in DSP and embedded programming and i've some doubts that i hope some of you could kindly answer. i've to do some profiling between DSP and ASIC/FPGA solutions. Im a FPGA guy so im lost with this DSP thing. 1) i'd like to know what do you think about the code i wrote, cause i feel it's not very "DSP optimized". I need to implement some sort of shiftregister or FIFO, b...


powerPC simulation

Started by san in comp.arch.embedded11 years ago 1 reply

Hello, am New to PCB board design cycle. Working on circuit having powerPC interfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do...

Hello, am New to PCB board design cycle. Working on circuit having powerPC interfaced with nand flash,FPGA,DDR and ethernet ASIC. I have to do the cycle accurate Functional simulation of the above circuit. How should i go for it? Queries: 1. Which tool i should use. 2. Do i need to convert schematics into verilog? 3. Do i need Models for all the components in the circuit. What is the p...


newbie: FIFOs and correlation algorithm in C for TI DSPs

Started by sebastian in comp.arch.embedded13 years ago 5 replies

hi, im a newbie in DSP and embedded programming and i've some doubts that i hope some of you could kindly answer. i've to do some profiling...

hi, im a newbie in DSP and embedded programming and i've some doubts that i hope some of you could kindly answer. i've to do some profiling between DSP and ASIC/FPGA solutions. Im a FPGA guy so im lost with this DSP thing. 1) i'd like to know what do you think about the code i wrote, cause i feel it's not very "DSP optimized". I need to implement some sort of shiftregister or FIFO, b...


Wanted: 5 people to look at an embedded book idea.

Started by larwe in comp.arch.embedded11 years ago 16 replies

Hello all, I'm working on the idea/presentation for my next book. It relates to retrogaming from an embedded developer's standpoint (not an...

Hello all, I'm working on the idea/presentation for my next book. It relates to retrogaming from an embedded developer's standpoint (not an emulation book, but more along the lines of "this is how you could develop a modern version of the 2D tile-based graphics ASIC in XYZ old arcade machine", and "this is how you can simulate a YM2159 synthesizer in VHDL"). I feel many of these circuits h...