SDRAM initialization

Started by Jim Stewart in comp.arch.embedded11 years ago 1 reply

I'm writing a new bios for an x86 processor with an integral SDRAM controller. I have it working with the SDRAM, but I'm troubled by a...

I'm writing a new bios for an x86 processor with an integral SDRAM controller. I have it working with the SDRAM, but I'm troubled by a specification in the SDRAM datasheet that requires a precharge of all banks to be issued upon powerup. As far as I can see, there is no way to run a specific SDRAM "command". Will a write to all banks accomplish the precharge?


SDRAM initialization sequence

Started by Lucky443 in comp.arch.embedded8 years ago

Hello, I am lucky, i am working with KMC board with NEC vr4131 processor and samsung K4S561632C SDRAM. my processor have an inbuilt SDRAM...

Hello, I am lucky, i am working with KMC board with NEC vr4131 processor and samsung K4S561632C SDRAM. my processor have an inbuilt SDRAM control unit. When we are initializaing the sdram, we have to follow the sequence(200us NOP, Precharge, 2xAuto Refresh and MRS) or initializaing the sdram controller's registers is enough. I tried by initializaing the SDRAM control unit registers ini...


AT91RM9200: Errors in transferring file into SDRAM via HyperTerminal (xmodem protocol)

Started by Mayank Kaushik in comp.arch.embedded12 years ago 9 replies

Hi everyone, ive been trying to interface a 16MB SDRAM (MT84LC8M16A2, 128Mbit, 2x16x4)with an AT91RM9200 on my custom board. The SDRAM and the...

Hi everyone, ive been trying to interface a 16MB SDRAM (MT84LC8M16A2, 128Mbit, 2x16x4)with an AT91RM9200 on my custom board. The SDRAM and the uC are placed close to each other on the 2-layer PCB (which me and my friend designed). I wrote a small SDRAM test program that sends a unique *byte* to each location of the SDRAM, and then reads it back..it ran without any errors, all values mat...


Using SDRAM

Started by rezaul in comp.arch.embedded8 years ago

Hi I am using a Kingston SDRAM 512MB for my virtex 2 pro development system. I am working on image filtering where i have to send the image file...

Hi I am using a Kingston SDRAM 512MB for my virtex 2 pro development system. I am working on image filtering where i have to send the image file to SDRAM from my PC. I am struck off in the following two steps: 1. How can I send the image file to the SDRAM. I can send some data values to SDRAM by the following code in EDK #define XPS_MEMRAM 0x60000000 //the starting address of the RAM as gi...


LPC2470 - SDRAM does not work

Started by Matej755 in comp.arch.embedded9 years ago 1 reply

Hi, my design "sample board" is connecting LPC2470 via 32 bit bus SRAM and SDRAM memory. SRAM works very well but SDRAM does not work. I use 2...

Hi, my design "sample board" is connecting LPC2470 via 32 bit bus SRAM and SDRAM memory. SRAM works very well but SDRAM does not work. I use 2 devices WINBOND W9816G6IH, 512Kx2Banksx16bits. I need urgenly help somebody... how to setting EMC and init SDRAM to start works. SDRAM gets eror reading data after write. I thing init procedure is no right. Thank you.


SDRAM Initialization Sequence

Started by mantaray in comp.arch.embedded8 years ago 6 replies

I am using the s3c4510b mcu, is it necessary to initialize the SDRAM in the bootup sequence or I can use the SDRAM directly after I set...

I am using the s3c4510b mcu, is it necessary to initialize the SDRAM in the bootup sequence or I can use the SDRAM directly after I set the special registers? If initialization of the SDRAM is required, what is the typical sequence like in assembly? Thanks!


DDR SDRAM

Started by Anonymous in comp.arch.embedded11 years ago 2 replies

Hi all, I'm designing an FPGA based board. I needed to add DDR-SDRAM. Is there a way to interface the SDRAM to the FPGA other than develop/buy...

Hi all, I'm designing an FPGA based board. I needed to add DDR-SDRAM. Is there a way to interface the SDRAM to the FPGA other than develop/buy a controller to put inside the FPGA? I mean: are there external DDR-SDRAM controllers? Cheers


Blackfin DSP SDRAM Memory

Started by Rob Reed in comp.arch.embedded14 years ago 1 reply

Hey All, I have a Blackfin 533 EZKit. I have ahd great success with every peripheral except the SDRAM. The doccumentation states that the...

Hey All, I have a Blackfin 533 EZKit. I have ahd great success with every peripheral except the SDRAM. The doccumentation states that the SDRAM bus is automatically configured so long as the auto-configure box is checked under Target Options(which it is) I must be oversimplifying this because now the SDRAM should be memory mapped from 0x0000 0000 to 0x07FF FFFF, but when I try to wri...


LPc2478 external Sdram initialization Help Needed

Started by Dravid in comp.arch.embedded8 years ago 1 reply

Hi all, Am using lpc2478 for 6.5 TFT LCD development in that am using 256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone...

Hi all, Am using lpc2478 for 6.5 TFT LCD development in that am using 256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone help me to solve the sdram initialization problem, i have attached the sdram init coding can anyone suggest me to solve the sdram initalizing problem. void sdramInit(void) { volatile unsigned short i,dummy; PINSEL5 &= 0XF0FCFCC0; PINSEL5 |= 0X...


LPc2478 external Sdram initialization Help Needed

Started by Dravid in comp.arch.embedded8 years ago 1 reply

Hi all, Am using lpc2478 for 6.5 TFT LCD development in that am using 256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone...

Hi all, Am using lpc2478 for 6.5 TFT LCD development in that am using 256Mb(K4S561632E-FROM SAMSUNG) SDRAM for LCD FRAME BUFFER. can anyone help me to solve the sdram initialization problem, i have attached the sdram init coding can anyone suggest me to solve the sdram initalizing problem. void sdramInit(void) { volatile unsigned short i,dummy; PINSEL5 &= 0XF0FCFCC0; PINSEL5 |= 0X050...


SAM7SE512 and external SDRAM

Started by RaceMouse in comp.arch.embedded10 years ago

Greetings, I am experimenting with FreeRTOS, external SDRAM, display and GCC on a SAM7SE512-EK. I am trying to put the code in internal...

Greetings, I am experimenting with FreeRTOS, external SDRAM, display and GCC on a SAM7SE512-EK. I am trying to put the code in internal flash and the data and bss sections in external SDRAM. The first thing my boot.s does is a call to a function that initialises the EBI and SDRAM. The internal SRAM is left unused. When I upload the SW via SAM-BA, all I need to do is to press the re...


SDRAM init & data bus

Started by aleksa in comp.arch.embedded7 years ago 4 replies

I need someone to confirm that the SDRAM does not use data bus to receive commands. Which means that I can mix the data bus in whatever way...

I need someone to confirm that the SDRAM does not use data bus to receive commands. Which means that I can mix the data bus in whatever way it suits me while am routing the PCB... right? (i.e., connect D0 on MCU do say, D5 on SDRAM) TIA P.S. I really don't like the guy who wrote 0xcafedede in SDRAM init on Atmel's examples.


A question about SDRAM's refresh!

Started by justnow in comp.arch.embedded12 years ago 3 replies

Hi! I am writing a SDRAM controller with VHDL.And I have blocks of data t store into the SDRAM very quickly,so SDRAM should be in BURST...

Hi! I am writing a SDRAM controller with VHDL.And I have blocks of data t store into the SDRAM very quickly,so SDRAM should be in BURST writ state,isn't it?My question is if the BURST write state continues a lon time(such as 1 second),should I stop BURST write and perform an AUT REFRESH operation per 64ms(because SDRAM should be refreshed per 64ms)?I other words,if I do a BURST write,can I o...


Mixing address lines in SDRAM.

Started by Wlad in comp.arch.embedded13 years ago 5 replies

Dear all, I have to boot-up a device based on Hitachi uP with external SDRAM (2x256Mb). The device was designed by somebody else and I only...

Dear all, I have to boot-up a device based on Hitachi uP with external SDRAM (2x256Mb). The device was designed by somebody else and I only have to get it working. However there is something that bothers me very much. Probably to easen PCB layout the designer has mixed data and address lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All other interface signals (RAS...


SDR SDRAM compability

Started by kalyanamsaritha in comp.arch.embedded9 years ago 1 reply

Could someone explain how I would go about determining if a particular SDR SDRAM (not DDR) is compatible with a CPU, AT91SAM9260 for...

Could someone explain how I would go about determining if a particular SDR SDRAM (not DDR) is compatible with a CPU, AT91SAM9260 for example. The cpu's Master Clock (MCK) runs at 100MHz which is the speed at which the SDRAM controller clock (SDCK) also runs. Does this automatically mean I should be looking for only PC100 rated SDR SDRAM? Any pointers would help the rest of us noobs out ...


Infineon TC1130 SDRAM controller.

Started by Anonymous in comp.arch.embedded10 years ago 3 replies

Hi, We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro Mt48LC4M32B2). Examining the memory signals with a logic...

Hi, We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro Mt48LC4M32B2). Examining the memory signals with a logic analyser, the SDRAM is being correctly written, refreshed and read. However, although we can see the expected data being output on a read command, the data does not reach the processor. The SDRAM setup code that we are using on our own board has been run...


Problem with SDRAM SAMSUNG K4S511632D-UC75

Started by oe1gca in comp.arch.embedded9 years ago 2 replies

Hi! With our current SDRAM initialization (in our boot code), sometimes the SDRAM does not work correctly after power-up reset. Every second...

Hi! With our current SDRAM initialization (in our boot code), sometimes the SDRAM does not work correctly after power-up reset. Every second quad-word can't be accessed (it seems that it can't be written). When the SDRAM is in this erroneous state after power-up, repetitive resets (not power-up) won't resolve the problem. Only a power-off/on cycle will resolve the problem. So I think, som...


AT91RM9200 problems to run from SDRam

Started by Reiner in comp.arch.embedded11 years ago 1 reply

Hi, We build own at91 board with an AT45DB642 and 64MB of SDRam. Above I'll describe some details. At45DB642 is attached to at91rm9200 on...

Hi, We build own at91 board with an AT45DB642 and 64MB of SDRam. Above I'll describe some details. At45DB642 is attached to at91rm9200 on CS0 and SDRam is using a 32bits of data path. We already tested both, and they are working without any kind of problem. We wrote data on At45DB642 and read it without errors, the same occured with SDRAM. What occurs is that when we run a program f...


AT91RM9200- SDRAM interface

Started by MaheshS in comp.arch.embedded12 years ago 1 reply

Hi, Can anyone explain why the address line A14 from AT91RM9200 is connected to NC pin of SDRAM (MT48LC8M16A2)? (reference:...

Hi, Can anyone explain why the address line A14 from AT91RM9200 is connected to NC pin of SDRAM (MT48LC8M16A2)? (reference: AT91RM9200ek-userguide, SDRAM interface section) Thanks S Mahesh.


Running code out of RAM

Started by Haran Vela in comp.arch.embedded13 years ago 17 replies

We are in the process of writing code to execut out of SDRAM for the first time in an upcoming project. Until now all our systems executed code...

We are in the process of writing code to execut out of SDRAM for the first time in an upcoming project. Until now all our systems executed code out of eprom or flash. However we need the speed that comes with running out of SDRAM but are concerned about SDRAM reliability issues and the possbility of rouge pointers corrupting SDRAM. Any RAM corruption will cause down time and reliability issue...