Hi, Microchip PIC 18f8722 USART2 Interrupt is not working - I have USART1 working fine with interrupts but cannot get interrupt on usart2 -...

Hi, Microchip PIC 18f8722 USART2 Interrupt is not working - I have USART1 working fine with interrupts but cannot get interrupt on usart2 - the RC2IF interrupt flag never gets set although data is coming into the rcreg2 register and i can read from it. Is there any special considerations I need to take into account? Global INT flag is enabled as well as all INTs on High priority. Code...

Even I write software for embedded systems for more than 10 years, there's an argument that from time to time let me think for hours and leave...

Even I write software for embedded systems for more than 10 years, there's an argument that from time to time let me think for hours and leave me with many doubts. Consider a simple embedded system based on a MCU (AVR8 or Cortex-Mx). The software is bare metal, without any OS. The main pattern is the well known mainloop (background code) that is interrupted by ISR. Interrupts are use...

I'm newish to Crossworks/CTL and need to confirm my understanding of the IRQ and FIQ stuff. So the question is... CTL redirects the IRQ...

I'm newish to Crossworks/CTL and need to confirm my understanding of the IRQ and FIQ stuff. So the question is... CTL redirects the IRQ handler to its own handler for ALL IRQ interrupts(correct?), where it calls the ISR in question and then CTL task handler stuff. If this is so, and I want to have a fast response to an EINT0 external interrupt then I have no choice but to accept the overhea...

Hi, I see a slide on rules of sleeping for RTOS. It says never sleep in atomic context (holding a lock, disabled interrupts etc.). It did not...

Hi, I see a slide on rules of sleeping for RTOS. It says never sleep in atomic context (holding a lock, disabled interrupts etc.). It did not mention semaphore in a sleeping state. I think semaphore is also an atomic context. It should not sleep when holding a semaphore. Is it right? Thanks,

Hi All, I have the following problem with the PIC18F4550. The EUSART is initialized as follows: movlw b'11111111' movwf...

Hi All, I have the following problem with the PIC18F4550. The EUSART is initialized as follows: movlw b'11111111' movwf TRISC,ACCESS movlw low(d'1249') movwf SPBRG,ACCESS movlw high(d'1249') movwf SPBRGH,ACCESS movlw b'00000100' movwf TXSTA,ACCESS movlw b'10000000' movwf RCSTA,ACCESS movlw b'00001000' ...

Using G++ (i.e. C++) for a Hitachi H8S micro, if we have inline functions to enable and disable interrupts using asm volatile like...

Using G++ (i.e. C++) for a Hitachi H8S micro, if we have inline functions to enable and disable interrupts using asm volatile like this inline void EnableInterrupts(void) { asm volatile("andc #0x3f,ccr" : : : "cc", "memory" ); } inline void DisableInterrupts(void) { asm volatile("orc #0xc0,ccr" : : : "cc", "memory" ); } does this mean that we can assume that all reads/ write...

OK ... a minor mystery ... While I've used PICs for many things, I've never made use of the SLEEP mode. For my 18f2620, the docs state...

OK ... a minor mystery ... While I've used PICs for many things, I've never made use of the SLEEP mode. For my 18f2620, the docs state : "All external interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up." ...

Hi! I've found a strange thing when using interrupts with GCC. When I compile the code and run it GCC tends to change the code depending in...

Hi! I've found a strange thing when using interrupts with GCC. When I compile the code and run it GCC tends to change the code depending in the content of the ISR-routine. When the interrupt occurs the return address + 0x04 is stored in lr register. This is as it should be. The first thing that happens in the ISR is a SUBS lr, lr, #0x04 to get the correct return address. The the ISR will...

I`m using AT91EB55 eval board. My interrupts rutines are based on functions which simply configure software buffers in order to store(by PDC)...

I`m using AT91EB55 eval board. My interrupts rutines are based on functions which simply configure software buffers in order to store(by PDC) there data from uart. If I put this functions(send_pdc(char *out_buff, int length) and recieve_pdc(char *in_buff, int length) ) into main function and send and receive some data then it works propertly but if i use receive function as a part of uart i...

Hi, I have a MCU project on a Toshiba MCU that only has 1 pin for external interrupt. However, I need 2 external interrupts from 2 devices....

Hi, I have a MCU project on a Toshiba MCU that only has 1 pin for external interrupt. However, I need 2 external interrupts from 2 devices. I'm wondering if there's a way to share that 1 pin between the 2 external interrupt inputs? I'm thinking of wiring the MCU pin directly to the inputs from the 2 devices A & B, and also wire those 2 devices to 2 other GPIO pins(say pin A and B). Then in...

We have a board with an old snapgear distro I'm trying to renew. The old linux kernel shows POSIX conformance testing by UNIFIX CARDBUS ...

We have a board with an old snapgear distro I'm trying to renew. The old linux kernel shows POSIX conformance testing by UNIFIX CARDBUS Bridge: primary=00, secondary=01 PCI Autoconfig: Found CardBus bridge, device 13 function 0 PCI Autoconfig: Found Bus 0, Device 13, Function 0 PCI Autoconfig: BAR 0, Mem, size=0x1000, address=0x4bfff000 Scanning sub bus 01, I/O 0x49000000, Mem 0x4bbff000 ...