Hi, I am using a spartan 3 xc3s4000 FPGA in my custom design which is interfaced with national gigabit PHYs DP83865dvh. It is actually...

Hi, I am using a spartan 3 xc3s4000 FPGA in my custom design which is interfaced with national gigabit PHYs DP83865dvh. It is actually an Ethernet mac and the design is like this: PHY A FPGA PHY B The problem is that sometimes, not always, i get one or two packet drops when i put the systems on test. I tested only one unit using chariot for throughput, no packet drops. But when i

Hi, I'm looking for an FPGA+DSP solution with small form factor (PC104 or less) for image processing. I thought about Spartan6 (for lvds to raw...

Hi, I'm looking for an FPGA+DSP solution with small form factor (PC104 or less) for image processing. I thought about Spartan6 (for lvds to raw conversion data) + TMS320C6457 (for image processing) I need also GbE and USB 2.0 link...I think that such PCB is really difficult to realize, so i'm looking for a company that has realized a similar product...any help? Thanks

Hello, designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated RocketIOs (Gigabit SerDes IOs) I am now facing the problem...

Hello, designing a motherboard featuring a Virtex-4 FX140 FPGA with 24 integrated RocketIOs (Gigabit SerDes IOs) I am now facing the problem of how to get the signals off the board in a most space-saving and elegant way? All 24 differential signals will be connected to some DACs outside the motherboard to convert the signals into the analog signal domain. In the definition of the inter...

Hello, I want to digitize some sensors and a touch panel with a FPGA. FPGA allow a certain flexibility but good external analog parts are...

Hello, I want to digitize some sensors and a touch panel with a FPGA. FPGA allow a certain flexibility but good external analog parts are necessary. In my context, the trouble comes from the screen's touch panel (classic low-value resistor type with 4 wires). I know that it is very sensitive to the environment (temperature, power supply, interferences...) and drift is very annoying (1% ...

I know this is the embedded forum, but with these parts especially the Fusion the design has more to do with embedded system design than FPGA. I...

I know this is the embedded forum, but with these parts especially the Fusion the design has more to do with embedded system design than FPGA. I just came back from the embedded systems conference and participated on these product seminars and discussion. The question I can not answer should I change over to one of the softcore FPGA based design concepts. I try to stick with one tool and n...

GAL,PAL,PLD, CPLD,FPGA, (what else...?) GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD :...

GAL,PAL,PLD, CPLD,FPGA, (what else...?) GAL : Generic Logic Array PAL : Programmable Array Logic PLD : Programmable Logic Device CPLD : Complex Programmable Logic Device FPGA : Field Programmable Gate Array Can someone explain with comparison what is the difference between all these GAL,PAL,PLD, CPLD,FPGA, (what else...?) logic units? Can all these units can be programmable with VH...

Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA's If one where to...

Hello, I am new to this FPGA stuff and I wanted to purchase a starter kit and get volume pricing for a few Xilinx FPGA's If one where to buy through Avnet or maybe NuHorizons, would anyone like to share your past experiences when working with them? It seems all they care are who you are, what company you work with, what you exactly are you doing. In other words, how many parts are y...

Hi All: I am in the process of development of code with some for controlling some FPGA's, I am hitting a road block where the Flash Prom size...

Hi All: I am in the process of development of code with some for controlling some FPGA's, I am hitting a road block where the Flash Prom size is smaller than the code size. Can anyone let me know if there are any compression algorithms for compressing data into flash and decompress when loading it into the FPGA's... If there are any links I would appreciate if you could direct to them T...

Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the...

Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the device or if it's advisable to use more than one due to the large package size...? Does it make any difference where I put the gclk input(s)? Thank you for your support... Regards Joe

Hello! My problem is similar with the post of spectrallypure schrieb. My colleagues are using different versions of QuartusII and my problem...

Hello! My problem is similar with the post of spectrallypure schrieb. My colleagues are using different versions of QuartusII and my problem is with the actual programming of the FPGA device. We've use QuartusII ver7.0 for the synthesis and generation of the *.pof and *.sof files. However, when these programming files are downloaded on an FPGA devices using QuartusII ver5.0, it seems that th...

Hi all, I?ve read the C code made by Xilinix to program a FPGA using an embedded microcontroller. The application is written to fit the 8051...

Hi all, I?ve read the C code made by Xilinix to program a FPGA using an embedded microcontroller. The application is written to fit the 8051 and I have to port it into a MSP430f1232 to program a Spartan 3. In the application description it says it is easy to port the code into others microcontroller and it is only needed to change few functions in the file ports.c but my GCC refuses to com

I want to design a space system and don't want to use airspace expensive fpga. considering space radiation I want to make this system fault...

I want to design a space system and don't want to use airspace expensive fpga. considering space radiation I want to make this system fault tolerant. ACTEL is flash-based but in program lost condition ( even with low probability ) it should be reprogrammed so a programing circuit is also needed. Xilinx or Altera are RAMbased but they have very small size EPROMs to store both hardware configur...

Dear Group, I=B4m new to FPGA, i.e. I=B4m about to start... Can anyone suggest a good development board for starters, or give me some...

Dear Group, I=B4m new to FPGA, i.e. I=B4m about to start... Can anyone suggest a good development board for starters, or give me some advice as to whether I should choose Xilinx or Altera... Is development on Altera / Xilinx much different from each other? Is it like PIC vs AVR vs Motorola??? best regards t=2E

Hi, I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL interface with an external COLDFIRE processor. Due to...

Hi, I'm looking for advice to implement on my FPGA (Xilinx SPARTAN 3A) a VHDL interface with an external COLDFIRE processor. Due to hardware considerations (not mine) I need to use 9 bits of address and 16 bits of datas, The following signals are available on my incoming pinout : TA, TEA, CS1, IRQ1 and R/W. Has anybody a clue where I can get some VHDL/Verilog code to help me? Thanks in adv...

Hi, a while ago I got a MCCB-3 board made by Prodrive (Netherlands). It is a 6U VME-Board with two PMC Slots and a Altera FPGA that is...

Hi, a while ago I got a MCCB-3 board made by Prodrive (Netherlands). It is a 6U VME-Board with two PMC Slots and a Altera FPGA that is apparently connected to the on-board PCI-66 via a couple of dual-port RAMs and a PCI-FIFO chip. I think this setup sounds pretty exciting but I have no idea about the pinout of the FPGA or the intended way to configure it. Does anyone know of this board ...

I know Xilinx and Altera have their SoC devices which are a bit high end with dual A9 type ARMs. I recently found out the Microsemi SoC which...

I know Xilinx and Altera have their SoC devices which are a bit high end with dual A9 type ARMs. I recently found out the Microsemi SoC which uses a CM3 can be bought for just $16 and a KickStart board is available for just $59. I like it. The FPGA fabric is flash based rather than SRAM so you don't need to configure it each time it powers up. The CPU has up to 512 kB flash and 144...

Hello, After completing the PART 1 of this tutorial you can now connect and verify the FX2 functioning as well as establish the End Point...

Hello, After completing the PART 1 of this tutorial you can now connect and verify the FX2 functioning as well as establish the End Point FIFO transfers in Bulk mode. However, all the transactions have taken place within the scope of FX2. Majority of the time, it is required to connect the FX2 with an external peripheral for instance FPGA or any micro processor to transmit and receive data...

Hi all, We are redesigning some 3U/6U Cards inserted in a chassis where backplane is specified to be driven by ABT logic (74ABT245/244), the...

Hi all, We are redesigning some 3U/6U Cards inserted in a chassis where backplane is specified to be driven by ABT logic (74ABT245/244), the problem we are facing is that the FPGA on some cards has 3v3 only IO's tolerant. Anyone here has got an elegant solution for interfacing +5V backplane (TTL ABT) to 3v3 device such as uP or FPGA's ? We have been looking for transceivers like 74...

Hi, What is memory mapping. If i memory mapped registers in my pheipheral,. The value written to them is teh value written to memory or it...

Hi, What is memory mapping. If i memory mapped registers in my pheipheral,. The value written to them is teh value written to memory or it will be written on physical registers in Pheripheral. Let me explain you cauz i know my description is bit confusing..... I have FPGA with a processor. Now i want to connect this processor with Custom IP (on FPGA) using Processor Local Bus. I know cus...

Hello, I want to learn how to design a digital system controlled from PC host and as a practical system to start from, I have chosen such...

Hello, I want to learn how to design a digital system controlled from PC host and as a practical system to start from, I have chosen such system: audio_signal1-> ADC-> digital_filter-> DAC-> audio_signal2 digital filter has to be FPGA-based and controlled from PC host running Windows XP. I mean that a user should be capable to choose a type of filter, bandwidth etc from GUI and load it to