Name this CPU (2)

Started by aleksa in comp.arch.embedded12 years ago 2 replies

* internal SRAM and FLASH ROM (protected from reading) * instruction set similar to x86, including: instruction mnemonics, ...

* internal SRAM and FLASH ROM (protected from reading) * instruction set similar to x86, including: instruction mnemonics, addressing modes, 8-16-32bit regs, read/write 8-16-32bit from/to internal/external memory, FPU * 32megs of addressable external memory * timers/counters, external IRQs, 32bits of memory-mapped I/O * pin-count around 100 (32 for data, 3...


"free" deallocation function with VisualDSP++ 4.5 for BF

Started by Jaime Andres Aranguren Cardona in comp.arch.embedded13 years ago 11 replies

Hi, Working with VisualDSP++ 4.5 for BF, the documentation...

Hi, Working with VisualDSP++ 4.5 for BF, the documentation says: free -------------------------------------------------------------------------------- deallocate memory Synopsis #include void free(void *ptr); Description The free function deallocates a pointer previously allocated to a range of memory (by calloc or malloc) to the free memory heap. If the pointer


Microprocessor address space and variables?

Started by Marco in comp.arch.embedded14 years ago 6 replies

Hallo, I must create a memory for a display lcd. This is part of a microcontroller based on a microprocessor. I thought to do it using a...

Hallo, I must create a memory for a display lcd. This is part of a microcontroller based on a microprocessor. I thought to do it using a variable, a matrix: display[X][Y] (the software video memory). This variable should exaclty stay into micrporcessor address space where I have mapped a ram (the hardware video memory) from 0x77200000 to 0x7720FFFF. In this way, working with my var...


Read EEPROM Memory on a mc9s12dg256 from Motorola

Started by Anonymous in comp.arch.embedded15 years ago 1 reply

Hi ! I have to write an EEPROM driver for an mc9s12dg256 from Motorola. Everything is fine, but i cant find a command ro read from the...

Hi ! I have to write an EEPROM driver for an mc9s12dg256 from Motorola. Everything is fine, but i cant find a command ro read from the eeprom memory. There are commands for Writing and erasing, but no Command for reading the memory. The Documentation from Motorola is real bad. Please help ! THX


Compact Flash Interfacing

Started by Al Clark in comp.arch.embedded15 years ago 9 replies

I am working on a compact flash design that will support Memory mode and I/O Mode but not True IDE Mode. The interface will be 16 bits...

I am working on a compact flash design that will support Memory mode and I/O Mode but not True IDE Mode. The interface will be 16 bits only. I can't see a compelling reason not to tie A0 & A5-A8 low. A9 is used in Attribute Memory. I have connections to REG, A10, A9, A4-A1. Starting with the Memory Mode interface, I added IORD & IOWR to support I/O Mode. I ignore IOCS since all interfa...


Not enough memory to declare global variable.

Started by Anonymous in comp.arch.embedded14 years ago 15 replies

Hi All, My MCU can't support me to declare large enough memory to store my byte arrary data, what can I do? Could you please...

Hi All, My MCU can't support me to declare large enough memory to store my byte arrary data, what can I do? Could you please advice? Thank you very much! Best regards, Boki.


Slightly[OT]---Memory-Mapped I/O

Started by Charles Jean in comp.arch.embedded15 years ago 4 replies

I just answered one here about this topic and it brought a question to my mine. Does anybody know of software that can be use on an...

I just answered one here about this topic and it brought a question to my mine. Does anybody know of software that can be use on an 80xxx series computer that provides a memory map of used/unused I/O port addresses? GRAVITY: It's not just a good idea-IT'S THE LAW!


Glueless memory

Started by Nitin Skandan in comp.arch.embedded16 years ago 2 replies

I have read that Motorola colfire series of processors provides a glueless memory interface. What exactly does this term mean. I tried google...

I have read that Motorola colfire series of processors provides a glueless memory interface. What exactly does this term mean. I tried google search but i could not get a satisfying answer. Please help Thank you NITIN S


Enough Space

Started by karthikbalaguru in comp.arch.embedded12 years ago 2 replies

Hi, Due to memory constraints, the application image is placed in 2 different flash memory . The image in the Flash Memory is already...

Hi, Due to memory constraints, the application image is placed in 2 different flash memory . The image in the Flash Memory is already of compressed format. In RAM, there is no enough space to accomodate both the parts together at the same time. How to overcome this scenario without increasing the RAM ? Is increasing the RAM , the only way to overcome this situation ? Thx in advans, ...


8051 architecture question

Started by JBrewster in comp.arch.embedded14 years ago 13 replies

I've been through a couple of 8051 tutorials but still have a very fuzzy view of its architecture. Could someone draw me a simple view of...

I've been through a couple of 8051 tutorials but still have a very fuzzy view of its architecture. Could someone draw me a simple view of it. From what I gather there is Program Memory and Data Memory. Withing Data Memory there are 1) General Purpose Registers (arranged in banks) 2) Bit Addressable Registers 3) Stack Space 4) SFR (Special Function Registers) Now are Program ...


Embedded flash memory issue with Linux 2.6.10 kernel....

Started by James Kimble in comp.arch.embedded11 years ago

I'm using the 2.6.10 kernel on a custom circuit board based on Freescales MCF5485evb evaluation board. My board has different flash memory...

I'm using the 2.6.10 kernel on a custom circuit board based on Freescales MCF5485evb evaluation board. My board has different flash memory than the evaluation board and so requires different flash drivers than the BSP that was provided with the board. The flash memory I am using is the Intel P33 (256P33B) NOR flash. I have two chips with the chip selects tied to the same logic line. The ...


Reduce/Optimize boot code memory C++

Started by srao in comp.arch.embedded3 years ago 39 replies

I need to cut down the size occupied by the boot code drastically to add in new code. The current memory occupied by boot code +application+ram...

I need to cut down the size occupied by the boot code drastically to add in new code. The current memory occupied by boot code +application+ram in an external flash memory chip is together 1MB. This cannot be increased. The boot code is located at the high address. All source code is written in C++. This is clearly an embedded/firmware query and would need help so as to how to optimize the sou...


EZUSB FX2LP transfer speed

Started by Anonymous in comp.arch.embedded13 years ago 6 replies

Hi out there, I still try to speed up my little curcuit that contains a CY68013A FX2LP Chip. I am able to transfer 3,5 Mb/s without any...

Hi out there, I still try to speed up my little curcuit that contains a CY68013A FX2LP Chip. I am able to transfer 3,5 Mb/s without any external memory. I want to transfer data with even higher speeds and want to extend memory for this. So can anyone explain which memory buffers I have to enlarge to reach higher transfer rates? Do I have to use bigger endpoint buffers? I am reading data fr...


Bootloader - erase flash memory

Started by Thomas Baier in comp.arch.embedded15 years ago 5 replies

Hi there, I've got a C164CI and I have to write a bootloader in assembly to load my Hex-Files into the Flash memory. I've got a 32-Byte...

Hi there, I've got a C164CI and I have to write a bootloader in assembly to load my Hex-Files into the Flash memory. I've got a 32-Byte primary loop that loads another loop, refered to as secondary loop, which should load the main prog and write it into the flash memory. Everything seems to work fine, as I've inserted some LED controll codes, and the code seems to work, but when I've finsh...


layout of c code image/binary in memory

Started by tele-commuter in comp.arch.embedded14 years ago 2 replies

Hi folks, I want to understand how exactly is an image(compiled c code and loaded into memory) stored in memory. What exactly is a linker...

Hi folks, I want to understand how exactly is an image(compiled c code and loaded into memory) stored in memory. What exactly is a linker script? I work with a lot of c code on a daily basis but I really don't understand : How exactly the sections like "text,bss,data etc." work? What exactly are they? I believe the linker script describes this layout. What exactl...


Flash Memory - Loading an Application of 2M size into 1M Flash memory

Started by KBG in comp.arch.embedded13 years ago 14 replies

Hi Friends, I have 1M flash memory allocated for Application. But the Application size exceeds the 1M limit (Application size is 2M). But,...

Hi Friends, I have 1M flash memory allocated for Application. But the Application size exceeds the 1M limit (Application size is 2M). But, now i cannot redesign the hardware and fit in any extra Flash Memories to resolve this size issue . I have RS232, Ethernet support on my board. My Bootloader is loading the application perfectly. ( I tried with a small application that spits some stri...


Rambus aims for 1 TeraByte per second memory bandwidth by 2010

Started by AirRaid in comp.arch.embedded12 years ago 23 replies

http://www.realworldtech.com/page.cfm?ArticleID=RWT120307033606&p=1 Rambus Sets the Bandwidth Bar at a Terabyte/Second Last week at...

http://www.realworldtech.com/page.cfm?ArticleID=RWT120307033606&p=1 Rambus Sets the Bandwidth Bar at a Terabyte/Second Last week at the annual Developer's Forum in Japan, Rambus announced an ambitious technology initiative that aims to create a 16 gigabit- per-second memory signaling layer that can sustain 1TB/s of bandwidth to a single memory controller by 2010. The Terabyte Bandwi...


Execute Disable Bit in Intel Core 2 Duo processor

Started by karthikbalaguru in comp.arch.embedded10 years ago 18 replies

Hi, It seems that Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks by allowing...

Hi, It seems that Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks by allowing the processor to classify areas in memory by where application code can execute and where it cannot. But, isn't it a normal functionality present in almost many of the processors that have memory classification as Read Only Memory and Read/Write Mem...


ElectricFence Exiting: mprotect() failed: Cannot allocate memory

Started by Bill in comp.arch.embedded11 years ago 25 replies

I am using electric fence 2.1.13 to try to find a memory allocation problem that occurs after my application runs for about 3 hours. When I...

I am using electric fence 2.1.13 to try to find a memory allocation problem that occurs after my application runs for about 3 hours. When I link to the electric fence library, I get "ElectricFence Exiting: mprotect() failed: Cannot allocate memory" during initialization. Could this be the source of the error that takes 3 hours to occur? I wonder because all I see at this point is a 12 byte ...


newbie question: Memory maped IO vs Port IO

Started by gt in comp.arch.embedded15 years ago 8 replies

Could someone explain memory mapped IO and Port IO? When should I use one or the other? why some devices support port IO only? thanks gt

Could someone explain memory mapped IO and Port IO? When should I use one or the other? why some devices support port IO only? thanks gt