pulse counter using LPC1768 proving to very challenging

Started by navman in comp.arch.embedded8 years ago 56 replies

Hi, I'm trying to counter some pulses (2-10usec width) using the LPC1768 Cortex-M3 microcontroller. There are 2 channels on which I have count...

Hi, I'm trying to counter some pulses (2-10usec width) using the LPC1768 Cortex-M3 microcontroller. There are 2 channels on which I have count the pulses on. I have to allow only pulses that are > =2us pulse width (so we cannot simply use the counter function). But it is turning out to be an incredibly difficult feat to achieve this on a 100MHz Cortex-M3. The problem arises when we try to mea


Cypress Add Turbo 8051 to PSoC (and Cortex too)

Started by -jg in comp.arch.embedded10 years ago

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz...

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz operation, and 120 part numbers Wide 1.7-5.5V operation.. LCD drive, 0.5V boost regulator... 0.1% voltage reference (14 ppm/=B0C) optional 24bx24b MAC - Cortex parts are 32K-256KF, and up to 64KRam, and 5.5V IO's well... (but no 32 bit timers?) Choic...


embedded processor with large memory support

Started by tns1 in comp.arch.embedded11 years ago 12 replies

I have been looking at current mainstream 32bit embedded processors for my project (ARM, cortex, PPC, coldfire, etc). I would sure like to find...

I have been looking at current mainstream 32bit embedded processors for my project (ARM, cortex, PPC, coldfire, etc). I would sure like to find a single device that has most of what I need, but I am running out of places to look. The main problem is memory support. The wish list is: cortex M3 40-60MIPS performance simple 3 banks of Flash 1MB internal, 512KB, 256KB 2 banks of RAM 1MB,...


Qestion about cycle count in ARM Cortex-A8?

Started by Anonymous in comp.arch.embedded6 years ago 11 replies

Hi, I am learning ARM Cortex-A8 CPU. In order to write optimized assembly code, I want to know the instruction scheduling. From A8 TRM, it...

Hi, I am learning ARM Cortex-A8 CPU. In order to write optimized assembly code, I want to know the instruction scheduling. From A8 TRM, it gives the following Table 16-4. I don't know how to use the cycle count, and its relationship with source and destination register. If cycle count is independent, the question is how to use it in scheduling. If cycle count is relevant to the s


Has someone tried to add interrupt support to Riscy Pygness?

Started by wzab in comp.arch.embedded8 years ago 22 replies

I just started to play with Riscy Pygness ( http://pygmy.utoh.org/riscy/cortex/ ) on target part of LPCXpresso 1769 board. The system works quite...

I just started to play with Riscy Pygness ( http://pygmy.utoh.org/riscy/cortex/ ) on target part of LPCXpresso 1769 board. The system works quite good as interactive environment for experimenting with ARM CORTEX processor, and seems to be an efficient development platform. The only thing which seems to be lacking is interrupt support. Well, I can write the interrupt service routine in assem...


Cortex A9 performance counters

Started by mart...@yahoo.com in comp.arch.embedded8 years ago

I have a specific question: Cortex A9 can count different types of events with Performance Monitoring Unit. What's exactly difference between...

I have a specific question: Cortex A9 can count different types of events with Performance Monitoring Unit. What's exactly difference between Integer Clock Enabled and Data Engine Clock Enabled types of events? And is there any chance to count all core clocks even if core makes WFI call? Thank you.


rad-hard MCUs?

Started by bo in comp.arch.embedded10 years ago 3 replies

Anyone know of a vendor that makes rad-hard ARM Cortex- Mx processors? including in SOC FPGAs? I know Actel makes rad-hard FPGA with embedded...

Anyone know of a vendor that makes rad-hard ARM Cortex- Mx processors? including in SOC FPGAs? I know Actel makes rad-hard FPGA with embedded ARM Cortex M1--but the processor is not rad-tolerant. Thanks, Paul --------------= Posted using GrabIt =---------------- ------= Binary Usenet downloading made easy =--------- -= Get GrabIt for free from http://www.shemes.com/ =-


Cortex M3 Low Cost Board Tools Recommendation Wanted.

Started by John in comp.arch.embedded9 years ago 8 replies

I am looking for a low cost platform for home Cortex M3 development. My main mandatory requirements are: 1. Under $250 total cost. 2. C...

I am looking for a low cost platform for home Cortex M3 development. My main mandatory requirements are: 1. Under $250 total cost. 2. C Demo code exists that will work out of the box. (I see some systems where many bugs need to be overcome to get a simple demo application to work. 3. Out of the box support for C.(Working C-Start / ctr0 that clear and initialises data are required by C,...


Real-life performance comparison, Microchip PIC32 and ARM Cortex M series

Started by Kvik in comp.arch.embedded7 years ago 2 replies

Hi Well, searching the web to make a fact based decision conserning which platform would have the best performance, PIC32 or Cortex M...

Hi Well, searching the web to make a fact based decision conserning which platform would have the best performance, PIC32 or Cortex M series does not provide consistent answers. Some sites provides graphs/tables that ARM has the upper hand, and others that microchip has So, what's the deal. Any golden answer? Performance: CoreMark uA/MHz Code size Portability Etc Thanks K...


Guest Webinar: Heterogeneous Multiprocessing with Android on NXP i.MX 7

Started by Matthew Do in comp.arch.embedded1 year ago

Asymmetric multiprocessing (AMP) systems fulfill the need for high performances and real-time by combining the responsiveness of a MCU (Cortex-M)...

Asymmetric multiprocessing (AMP) systems fulfill the need for high performances and real-time by combining the responsiveness of a MCU (Cortex-M) with the processing power of an application processor which runs a full OS. This webinar presents a technical overview on asymmetric multiprocessing and its implementation on an NXP i.MX 7 Colibri System on Module running Android on the MPU (Cortex-A,...


New ARM Cortex Microcontrollers from STMicroelectronics have More of Everything

Started by Bill Giovino in comp.arch.embedded11 years ago

STMicroelectronics has announced a significant expansion of their STM32 ARM Cortex product...

STMicroelectronics has announced a significant expansion of their STM32 ARM Cortex product family: http://microcontroller.com/news/arm_cortex_stm1.asp New features include five USARTs on one microcontroller, a DAC, new memory interfaces, and up to 512KBytes of Flash. Microcontrollers in this product family draw a miserly 36mA at 72MHz (core) run mode. This original announcement is here...


First Cortex-M3 MCUs available

Started by Wilco Dijkstra in comp.arch.embedded13 years ago 54 replies

Luminary Micro Announces 32-bit Microcontrollers for $1.00 - First to Launch Products Based on the ARM Cortex-M3...

Luminary Micro Announces 32-bit Microcontrollers for $1.00 - First to Launch Products Based on the ARM Cortex-M3 Processor http://www.chron.com/disp/story.mpl/conws/3750146.html More details and specs: http://www.luminarymicro.com/index.php?option=com_content&task=view&id=37&Itemid=73 The long awaited ARMv7M architecture reference including full Thumb-2 details: http://www.lumin...


A timer driver for Cortex-M0+... it rarely doesn't work

Started by pozz in comp.arch.embedded2 years ago 32 replies

I don't know if it is an issue specific to Atmel SAMC21 Cortex-M0+ devices or not. I wrote a simple timer driver: a 32-bits hw counter...

I don't know if it is an issue specific to Atmel SAMC21 Cortex-M0+ devices or not. I wrote a simple timer driver: a 32-bits hw counter clocked at 875kHz (14MHz/16) that triggers an interrupt on overflow (every 1h 21'). In the interrupt I increment the 32-bits global variable _ticks_high. The 64-bits number composed by _ticks_high (upper 32-bits) and the hw counter (lower 32-bits) is m...


Play an audio stream with a Cortex-M0+

Started by pozz in comp.arch.embedded2 years ago 3 replies

I need to reproduce a short audio stream with a Cortex-M0+ MCU (it's SAM D21E from Atmel/Microchip). The audio bitstream will be stored in an...

I need to reproduce a short audio stream with a Cortex-M0+ MCU (it's SAM D21E from Atmel/Microchip). The audio bitstream will be stored in an external SPI Flash memory (I need to manage many short audio streams, so the internal Flash memory is not sufficient). SAMD21 features DAC, SPI and DMA. The audio will not be high-fidelity. 8 bits at 8kHz sampling frequency is enough. I didn't m...


New ARM Cortex Microcontroller Product Family from STMicroelectronics

Started by Bill Giovino in comp.arch.embedded12 years ago 90 replies

http://www.microcontroller.com/news/arm_cortex_stm.asp STMicroelectronics has introduced the new STM32 microcontroller family, based on...

http://www.microcontroller.com/news/arm_cortex_stm.asp STMicroelectronics has introduced the new STM32 microcontroller family, based on the Harvard architecture ARM Cortex. Article includes a roadmap and a useful chart of the STM32 low power operation, which is as low as 0.5mA/MHz. Regards Bill Giovino Executive Editor http://Microcontroller.com


Cortex M3: CPU Context to Retention RAM

Started by Anonymous in comp.arch.embedded4 years ago 6 replies

Hi, I am looking for some pointers, links or apps notes. Consider a Cortex M3 based system which has a deep sleep mode whereby CPU core is...

Hi, I am looking for some pointers, links or apps notes. Consider a Cortex M3 based system which has a deep sleep mode whereby CPU core is powered down, but the system RAM retains state (retention RAM). Prior to entering deep sleep, I would like to save "CPU Context" to give me the fastest startup response after a wake event. (I think that on some older ARM CPUs, this was called "dor


STMicroelectronics Introduces ST SPEAr1310 Microcontroller with Dual-Core Cortex

Started by Bill Giovino in comp.arch.embedded9 years ago 4 replies

http://www.microcontroller.com/news/ST_SPEAr1310.asp This has dual ARM Cortex-A9 cores and a DDR3 memory interface. Also, multiple Ethernet...

http://www.microcontroller.com/news/ST_SPEAr1310.asp This has dual ARM Cortex-A9 cores and a DDR3 memory interface. Also, multiple Ethernet interfaces, three USB ports, CAN, I2C, touchscreen interface, and a bunch of other stuff. From STMicroelectronics: http://www.microcontroller.com/STMicroelectronics.htm Above article includes a block diagram. Bill Giovino http://Microcontrolle...


Ration between MCU and JTAG/SWD clock (Cortex-M and others)?

Started by Uwe Bonnes in comp.arch.embedded3 years ago 12 replies

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but...

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but facts for other archs are welcome. Information floating aound in the net tells abound a factor of 6, but some people tell about successfull SWD communication even with a MCU clock much slower than the SWD clock. Thanks -- Uwe Bonnes ...


What's the differences for TI AM335x and AM437x?

Started by Mei Zhang in comp.arch.embedded4 years ago 3 replies

Our company MYIR has recently released a new product Rico Board based on TI AM437x. http://www.myirtech.com/list.asp?id=510 Compared to...

Our company MYIR has recently released a new product Rico Board based on TI AM437x. http://www.myirtech.com/list.asp?id=510 Compared to AM335x processor, I think the main differences might be the ARM core and camera support. The AM437x is using ARM Cortex-A9 core while the AM335x is using Cortex-A8. The AM437x can support camera but AM335x can not. Do you know any other d


OFFTOPIC?: arm-linux-gnueabi-gdb error with cortex-m3 code

Started by jackbenimble in comp.arch.embedded6 years ago 9 replies

So I have encountered a very odd gdb error that I cant make sense of. I am using version 4.4.5 of the gcc tools (arm-linux-gnueabi) and version...

So I have encountered a very odd gdb error that I cant make sense of. I am using version 4.4.5 of the gcc tools (arm-linux-gnueabi) and version 7.0.1 of the gdb (arm-linux-gnueabi) debugger. I am using stm32f103 cortex-m3 board Basically gdb seems to be clobbering the values passed to functions. Heres an example: Breakpoint 1, main () at apps/core/core_test.c:46 46 wdTemp = wdT...