Hi, Does anyone know of a small cheap ARM Cortex dev board with all of Bluetooth, Wifi and CAN onboard ? STM preferred but I can't find...

Hi, Does anyone know of a small cheap ARM Cortex dev board with all of Bluetooth, Wifi and CAN onboard ? STM preferred but I can't find anything suitable in their lineup. Something with good SW support preferred to save me a porting expedition... Thanks, Mike

Hi, I'm looking for a cheap dev kit with an ARM Cortex CPU and both a 3-axis gyro and a 3-axis accelerometer. Anyone know of such a board ? I...

Hi, I'm looking for a cheap dev kit with an ARM Cortex CPU and both a 3-axis gyro and a 3-axis accelerometer. Anyone know of such a board ? I really don't need much else apart from the ability to drive 3 PWM channels as outputs. Project is a stabilised camera platform for use on a boat. Thanks, Boo

Hi, Question as title : I have an existing product that has an ARM Cortex M3 CPU and which I need to retrofit with assymetric crypto to send...

Hi, Question as title : I have an existing product that has an ARM Cortex M3 CPU and which I need to retrofit with assymetric crypto to send small amounts of encrypted data. The CPU I am landed with doen't have a crypto module available and cannot be changed so I need a C library that can do assymetric crypto (key exchange etc) and still run, even if slowly) in a restricted mem

Here[1] you will find the vector table of Cortex-M3 core. There are 4 vectors (16 bytes) that are named "Reserved" (plus one more at index...

Here[1] you will find the vector table of Cortex-M3 core. There are 4 vectors (16 bytes) that are named "Reserved" (plus one more at index 13). Do you think they can be used for custom purposes? The word "Reserved" seems this can't be done. I'd like to use those vectors, that are in the non-volatile Flash memory, to store some data. In my case, I will save the MAC address (6 bytes...

Hi, I'm trying to counter some pulses (2-10usec width) using the LPC1768 Cortex-M3 microcontroller. There are 2 channels on which I have count...

Hi, I'm trying to counter some pulses (2-10usec width) using the LPC1768 Cortex-M3 microcontroller. There are 2 channels on which I have count the pulses on. I have to allow only pulses that are > =2us pulse width (so we cannot simply use the counter function). But it is turning out to be an incredibly difficult feat to achieve this on a 100MHz Cortex-M3. The problem arises when we try to mea

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz...

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz operation, and 120 part numbers Wide 1.7-5.5V operation.. LCD drive, 0.5V boost regulator... 0.1% voltage reference (14 ppm/=B0C) optional 24bx24b MAC - Cortex parts are 32K-256KF, and up to 64KRam, and 5.5V IO's well... (but no 32 bit timers?) Choic...

I have been looking at current mainstream 32bit embedded processors for my project (ARM, cortex, PPC, coldfire, etc). I would sure like to find...

I have been looking at current mainstream 32bit embedded processors for my project (ARM, cortex, PPC, coldfire, etc). I would sure like to find a single device that has most of what I need, but I am running out of places to look. The main problem is memory support. The wish list is: cortex M3 40-60MIPS performance simple 3 banks of Flash 1MB internal, 512KB, 256KB 2 banks of RAM 1MB,...

Hi, I am learning ARM Cortex-A8 CPU. In order to write optimized assembly code, I want to know the instruction scheduling. From A8 TRM, it...

Hi, I am learning ARM Cortex-A8 CPU. In order to write optimized assembly code, I want to know the instruction scheduling. From A8 TRM, it gives the following Table 16-4. I don't know how to use the cycle count, and its relationship with source and destination register. If cycle count is independent, the question is how to use it in scheduling. If cycle count is relevant to the s

I just started to play with Riscy Pygness ( http://pygmy.utoh.org/riscy/cortex/ ) on target part of LPCXpresso 1769 board. The system works quite...

I just started to play with Riscy Pygness ( http://pygmy.utoh.org/riscy/cortex/ ) on target part of LPCXpresso 1769 board. The system works quite good as interactive environment for experimenting with ARM CORTEX processor, and seems to be an efficient development platform. The only thing which seems to be lacking is interrupt support. Well, I can write the interrupt service routine in assem...

Anyone know of a vendor that makes rad-hard ARM Cortex- Mx processors? including in SOC FPGAs? I know Actel makes rad-hard FPGA with embedded...

Anyone know of a vendor that makes rad-hard ARM Cortex- Mx processors? including in SOC FPGAs? I know Actel makes rad-hard FPGA with embedded ARM Cortex M1--but the processor is not rad-tolerant. Thanks, Paul --------------= Posted using GrabIt =---------------- ------= Binary Usenet downloading made easy =--------- -= Get GrabIt for free from http://www.shemes.com/ =-

Hi Well, searching the web to make a fact based decision conserning which platform would have the best performance, PIC32 or Cortex M...

Hi Well, searching the web to make a fact based decision conserning which platform would have the best performance, PIC32 or Cortex M series does not provide consistent answers. Some sites provides graphs/tables that ARM has the upper hand, and others that microchip has So, what's the deal. Any golden answer? Performance: CoreMark uA/MHz Code size Portability Etc Thanks K...

I am looking for a low cost platform for home Cortex M3 development. My main mandatory requirements are: 1. Under $250 total cost. 2. C...

I am looking for a low cost platform for home Cortex M3 development. My main mandatory requirements are: 1. Under $250 total cost. 2. C Demo code exists that will work out of the box. (I see some systems where many bugs need to be overcome to get a simple demo application to work. 3. Out of the box support for C.(Working C-Start / ctr0 that clear and initialises data are required by C,...

Asymmetric multiprocessing (AMP) systems fulfill the need for high performances and real-time by combining the responsiveness of a MCU (Cortex-M)...

Asymmetric multiprocessing (AMP) systems fulfill the need for high performances and real-time by combining the responsiveness of a MCU (Cortex-M) with the processing power of an application processor which runs a full OS. This webinar presents a technical overview on asymmetric multiprocessing and its implementation on an NXP i.MX 7 Colibri System on Module running Android on the MPU (Cortex-A,...

Luminary Micro Announces 32-bit Microcontrollers for $1.00 - First to Launch Products Based on the ARM Cortex-M3...

Luminary Micro Announces 32-bit Microcontrollers for $1.00 - First to Launch Products Based on the ARM Cortex-M3 Processor http://www.chron.com/disp/story.mpl/conws/3750146.html More details and specs: http://www.luminarymicro.com/index.php?option=com_content&task=view&id=37&Itemid=73 The long awaited ARMv7M architecture reference including full Thumb-2 details: http://www.lumin...

I don't know if it is an issue specific to Atmel SAMC21 Cortex-M0+ devices or not. I wrote a simple timer driver: a 32-bits hw counter...

I don't know if it is an issue specific to Atmel SAMC21 Cortex-M0+ devices or not. I wrote a simple timer driver: a 32-bits hw counter clocked at 875kHz (14MHz/16) that triggers an interrupt on overflow (every 1h 21'). In the interrupt I increment the 32-bits global variable _ticks_high. The 64-bits number composed by _ticks_high (upper 32-bits) and the hw counter (lower 32-bits) is m...

I need to reproduce a short audio stream with a Cortex-M0+ MCU (it's SAM D21E from Atmel/Microchip). The audio bitstream will be stored in an...

I need to reproduce a short audio stream with a Cortex-M0+ MCU (it's SAM D21E from Atmel/Microchip). The audio bitstream will be stored in an external SPI Flash memory (I need to manage many short audio streams, so the internal Flash memory is not sufficient). SAMD21 features DAC, SPI and DMA. The audio will not be high-fidelity. 8 bits at 8kHz sampling frequency is enough. I didn't m...

http://www.microcontroller.com/news/arm_cortex_stm.asp STMicroelectronics has introduced the new STM32 microcontroller family, based on...

http://www.microcontroller.com/news/arm_cortex_stm.asp STMicroelectronics has introduced the new STM32 microcontroller family, based on the Harvard architecture ARM Cortex. Article includes a roadmap and a useful chart of the STM32 low power operation, which is as low as 0.5mA/MHz. Regards Bill Giovino Executive Editor http://Microcontroller.com

Hi, I am looking for some pointers, links or apps notes. Consider a Cortex M3 based system which has a deep sleep mode whereby CPU core is...

Hi, I am looking for some pointers, links or apps notes. Consider a Cortex M3 based system which has a deep sleep mode whereby CPU core is powered down, but the system RAM retains state (retention RAM). Prior to entering deep sleep, I would like to save "CPU Context" to give me the fastest startup response after a wake event. (I think that on some older ARM CPUs, this was called "dor

http://www.microcontroller.com/news/ST_SPEAr1310.asp This has dual ARM Cortex-A9 cores and a DDR3 memory interface. Also, multiple Ethernet...

http://www.microcontroller.com/news/ST_SPEAr1310.asp This has dual ARM Cortex-A9 cores and a DDR3 memory interface. Also, multiple Ethernet interfaces, three USB ports, CAN, I2C, touchscreen interface, and a bunch of other stuff. From STMicroelectronics: http://www.microcontroller.com/STMicroelectronics.htm Above article includes a block diagram. Bill Giovino http://Microcontrolle...

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but...

Hello, has anybody hard facts what the requirements for the ration between Jtag/SWD clock and MCU clock is. Main interest is for Cortex-M, but facts for other archs are welcome. Information floating aound in the net tells abound a factor of 6, but some people tell about successfull SWD communication even with a MCU clock much slower than the SWD clock. Thanks -- Uwe Bonnes ...