"mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or...

"mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx- specific (through component instantiation) multi-port memories. "mprfgen" was written during the course of a few days back in 2007. I guess I'm releasing this now since it is still useful and relevant. I would appreciate any comments and suggestions rega...

http://bknpk.no-ip.biz/cpu_8051_ver/top.html # Stable Design: The design is translated from a VHDL dalton...

http://bknpk.no-ip.biz/cpu_8051_ver/top.html # Stable Design: The design is translated from a VHDL dalton project http://www.cs.ucr.edu/~dalton/i8051/i8051syn. # Small Design: Consumes only 324 Flip-Flops: map report # Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report

Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for...

Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for non- trivial work. HercuLeS allows you to synthesize ANSI C code (certain rules apply) to RTL VHDL. HercuLeS is named after the homonymous constellation and not after the demigod. You can find information on HercuLeS here: http://www.nkavvadias.com/he...

hi, I'm writing vhdl code for TELIT GE864-GPS module, my aim is to send an sms to a particular number whenever the network is available, the data...

hi, I'm writing vhdl code for TELIT GE864-GPS module, my aim is to send an sms to a particular number whenever the network is available, the data in the sms will be changing, but what i don't understand is, how to find through programming (are there any commands) whether the network is available for the modem or not, I have to use the modem in the remote places.

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave,...

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave, ramp, triangular and square wave generator which outputs required wave of required amplitude and required frequency The FPGA is connected with DAC thru I2C bus.. The development board (nanoboard) has on- board freq of 20 mhz...now the dac being co...

Hi, I have written a VHDL model of a pic18 micro, and I have written self test code which has run correctly in an FPGA implementation. I am...

Hi, I have written a VHDL model of a pic18 micro, and I have written self test code which has run correctly in an FPGA implementation. I am looking for additional test code to run on the model to verify that it is operating correctly. Thanks, Scott L Baker

Hi, I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope...

Hi, I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope to hear some noise. My VHDL code, tested on PeakVHDL simulator does generate the waveform and is pasted at the far bottom. The problem is that the code does not compile on Xilinx because "WAIT for 2.5 ns" is not supported on Xilinx Spartan II for...

Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa....

Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa. The core should acts as a USB device for the PC. The core is intended for an FPGA projects where an "easy" interface to a PC is needed. Higher data rates as defined by the 3.0 standard should be possible with the implementation. Questions are...

Hi! Sorry if this is not the right group for the question but it seems to be the closest to the topic I could find. The problem is...

Hi! Sorry if this is not the right group for the question but it seems to be the closest to the topic I could find. The problem is this: I'm trying to implement a simple processor-based project on the NanoBoard using Altium Designer. I'm using TSK51 and external memory chip (128K SRAM) on the NanoBoard and my task is to connect them by writing a VHDL memory controller. I've created a...

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4...

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4 month's ego with an ML405 Xilinx Virtex 4 board and I wanted now to implement a Software Defined Radio (SDR). I understand everything that relates to SDR (theory, operation, Etc..) Very good. Likewise, I also understand VHDL and VERILOG. Now I would li...

Hi, I'm currently working on a interface to a CF-Card via a System ACE Controller. I was wondering if somebody already did a create a "Model"...

Hi, I'm currently working on a interface to a CF-Card via a System ACE Controller. I was wondering if somebody already did a create a "Model" of a System ACE Controller to use it in some testbenches to verify the interface is working correctly? Regards, Andreas

GHDL is free simulator. I found this tool very useful. GHDL is also capable simulating the free LEON processor. Presently, if the VCD option is...

GHDL is free simulator. I found this tool very useful. GHDL is also capable simulating the free LEON processor. Presently, if the VCD option is enabled, all signals of the design are recorded. This impacts the performance and requires large disk space. I generate my own form the VHDL code (example: probe_i2c_slv.vhd). This way it is easy to select what signals to dump and on what time. Mor...

I am trying to put some value on FD[0..15] by PORT B and PORT D. The FD[0..7] is connected to LEDs on Spartan board.But I am having problem...

I am trying to put some value on FD[0..15] by PORT B and PORT D. The FD[0..7] is connected to LEDs on Spartan board.But I am having problem as these values are not shown up. The code on kiel is compiling fine and I can upload the firmware onto EZ USB FX2 without any problem but the desired values are not displayed. BTW, i use vhdl code to make reset for board. Here is my code: #define ALLOCAT...

Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on...

Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on a Xilinx Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect in the target application. Therefore I made an analysis with the Xilinx Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying results. Now I'd ...

Hello, I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA via FT2232H in FT245 synchronuous FIFO mode workd perfect....

Hello, I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA via FT2232H in FT245 synchronuous FIFO mode workd perfect. However, I've got some problems with reading from FPGA to PC in this mode. Below is a part of my VHDL code responsible for it: USB_CLK: in std_logic; RST : in std_logic; TXE_n : in std_logic; WR_n : out std_logic; USB_DATA: inout std

TTA-Based Co-design Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport...

TTA-Based Co-design Environment (TCE) is a toolset for designing application-specific processors (ASP) based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the ...

Hello there, one of new members around here. I've got a problem while i try to retrieve/pass over some values to memory. I use EDK 9.1 and a...

Hello there, one of new members around here. I've got a problem while i try to retrieve/pass over some values to memory. I use EDK 9.1 and a system of microblaze, opb bus and opb bram memory. I try to retrieve some values from memory through a vhdl testbench, which is port mapped in the PORT B of Bram (by making Bram's PORT B external) and then write back these contents in other blocks - a...

Hello, so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ and developing a completely new instruction set, along with an architecture,...

Hello, so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ and developing a completely new instruction set, along with an architecture, tools etc... in JavaScript (before I translate to C and VHDL). An overall description of the core is available at http://f-cpu.seul.org/whygee/vspsim/doc/vsp.html [note that it is always under construction so some parts don't work] My question : ...

Hi! I am writing a SDRAM controller with VHDL.And I have blocks of data t store into the SDRAM very quickly,so SDRAM should be in BURST...

Hi! I am writing a SDRAM controller with VHDL.And I have blocks of data t store into the SDRAM very quickly,so SDRAM should be in BURST writ state,isn't it?My question is if the BURST write state continues a lon time(such as 1 second),should I stop BURST write and perform an AUT REFRESH operation per 64ms(because SDRAM should be refreshed per 64ms)?I other words,if I do a BURST write,can I o...

The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises...

The LOOPGEN IP collection provides fast hardware architectures for implementing nested loop structures. The collection comprises of three different architectures (variants), namely: - HWLU, a mixed-level structural/RTL architecture, - IXGENB, a behavioral-level and - IXGENR, a high-performance, pure RTL description of a more generalized form of the architecture. Hardware looping archite...