Its not a big problem but annoying nonetheless. I installed the ISE 8.2 last week and have been using the view rtl schematic and view technology...

Its not a big problem but annoying nonetheless. I installed the ISE 8.2 last week and have been using the view rtl schematic and view technology schematic features just fine since my install. Today, however, when I open up the schematics the page is blank. I have to zoom in or zoom to screen to see anything. And this doesnt always work. Of course, if it does work then I have to zoom back...

"mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or...

"mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx- specific (through component instantiation) multi-port memories. "mprfgen" was written during the course of a few days back in 2007. I guess I'm releasing this now since it is still useful and relevant. I would appreciate any comments and suggestions rega...

http://bknpk.no-ip.biz/cpu_8051_ver/top.html # Stable Design: The design is translated from a VHDL dalton...

http://bknpk.no-ip.biz/cpu_8051_ver/top.html # Stable Design: The design is translated from a VHDL dalton project http://www.cs.ucr.edu/~dalton/i8051/i8051syn. # Small Design: Consumes only 324 Flip-Flops: map report # Fast Design: 50MHz for a xc4vlx25-10 XILINX device: timing report

Hello, does enybody use Xilinx Uartlite hi -level driver. I spent so much time trying to make it works, and it still don't want to. I don't...

Hello, does enybody use Xilinx Uartlite hi -level driver. I spent so much time trying to make it works, and it still don't want to. I don't understand how it works, and the example in driver's directory tells me not much. I'm trying to send/recive data to/from PC to Microblaze using UARTLite. I want to use driver in interrupt mode (I guess I want), so the processor stops running program and...

Hi all, I have designed (on paper ) a radio system with the following components - 1) ATmega1280 - Responsible for talking to 3 uarts , the...

Hi all, I have designed (on paper ) a radio system with the following components - 1) ATmega1280 - Responsible for talking to 3 uarts , the FPGA and Ethernet controller. 2) A Xilinx FPGA interfaced with the Atmega - responsible for digital modulation , demodulation of radio signals. It also interfaces with the Ethernet controller for high bit rate. the decision behind the ATmega was ...

I am drafting designer into the Circuit Cellar design contest, ($10,000 splits three ways). We will be fitting an RF transponder into a...

I am drafting designer into the Circuit Cellar design contest, ($10,000 splits three ways). We will be fitting an RF transponder into a cell phone (with the orginal board removed). So, we need experts in the following area. ISM band FSK RF transceiver TDA5100/5210 TRF6903 FPGA/CPLD LCD controller (100x100) Xilinx Spartian/Cool Runner ARM LM3SXXX (required) I recome...

I need to implement a communication between an starter kit (Xilinx Spartan3E) and a remote computer trought internet. The final application is...

I need to implement a communication between an starter kit (Xilinx Spartan3E) and a remote computer trought internet. The final application is a remote control for a home system (domotic System) all that i need is to reach the communication between the two nodes using ethernet interface in the fpga board, and internet connection in the computer (Windows XP) without additional software, only b...

I have a jtag programmer for xilinx devices ,is this a standard interface ? Can i use this device to program other devices with a JTAG interface...

I have a jtag programmer for xilinx devices ,is this a standard interface ? Can i use this device to program other devices with a JTAG interface (eg ARM ) ? Or do i need a dedicated tjag interface for every Jtag device i intend to use ? (whats the use of a JTAG standard then ?) Johan

Hi,to all i have built a kind of...thing with the purpose to program a Flash memory from PC parallel via a CPLD The Cpld i used is a...

Hi,to all i have built a kind of...thing with the purpose to program a Flash memory from PC parallel via a CPLD The Cpld i used is a Xilinx xc95144 and the flash that i got scraped from surplus(maybe a dvd) is HY29LV160 www.hynix.com/inc/pdfDownload.jsp?path=/upload/products/gl/products/flash/down/HY29LV160.pdf I did the programming software in visual basic,and it looks that i can ...

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the...

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the HTG-V4PCIe evaluation board, which is a Xilinx Virtex-4 PCI Express Development Board from HighTech Global (http://www.hitechglobal.com/boards/v4pcie.htm). It features the Marvell Alaska 88E1111 Gigabit-Ethernet PHY which I use in combination with t...

Hi, are there any fpga/embedded/pcb design courses online or in toronto that i as a newbie could take as a newbie. I'm new to the field of...

Hi, are there any fpga/embedded/pcb design courses online or in toronto that i as a newbie could take as a newbie. I'm new to the field of fpga and I have got a xilinx starter kit with the spartan III chip. I'd prefer to go through a full fledged instructor led course where i learn hardware design. Does anything like that exists? Thank you in advance for your advice.

This is somewhat OT - more on networking. I am using a Gigabit Ethernet MAC chip from Marv***, which claims full line rate (compliance to IEEE...

This is somewhat OT - more on networking. I am using a Gigabit Ethernet MAC chip from Marv***, which claims full line rate (compliance to IEEE 802.3ab). It has an integrated GMAC, PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we connect it to a Spartan IIe-300 with a Xilinx PCI Logicore. Everything works in the FPGA, PCI read/write transactions, but we cannot achiev...

I'm cleaning out some dev boards that have been sitting on my shelf for too long. This ML403 embedded dev kit has been powered up once (to test...

I'm cleaning out some dev boards that have been sitting on my shelf for too long. This ML403 embedded dev kit has been powered up once (to test the included Linux BSP, and to blink an LED), and then put on the shelf for a project that I never got around to. Hoping to find a good home for it: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=270310045310 In addition, the full licenses ...

ML403 - Virtex4 - PPC405 - Xilinx EDK V10.1 Hi, I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). ...

ML403 - Virtex4 - PPC405 - Xilinx EDK V10.1 Hi, I have a working PPC405 design to which I want to add the APU FPU IP (enough acronyms?). I have used the wizard to configure basically the same design, but with the FPU included - this is therefore the default wizard hardware design with no manual tinkering from me on either the hardware or software libraries. This now runs non floati...

working with xilinx edk. I have a sdram of 32M, when I tried to copy data from flash to sdram, it works well only when the accouts is less...

working with xilinx edk. I have a sdram of 32M, when I tried to copy data from flash to sdram, it works well only when the accouts is less than 8K, when i copy data, which is more than 8K,it is wrong. it just repeatly copy a little data to sdram,what is the problem should be? I am sure my flash works well.

Hi, I implemented an Aurora link layer using EDK.Now I am concerned about reliability and want to implement a 64-Bit or 32-Bit Hamming Code...

Hi, I implemented an Aurora link layer using EDK.Now I am concerned about reliability and want to implement a 64-Bit or 32-Bit Hamming Code to enable error detection and correction. Now I am wondering if that makes sense anyway, because if there are bit errors the 8B/10B coding featured in Aurora would dismiss erroneous data words anyway and the Hamming Code would not work. Please cor...

Unable to query target part layout!!! When I work with the xilinx edk(ver8.1), after buttoning down the ? download bitstream?, I want to...

Unable to query target part layout!!! When I work with the xilinx edk(ver8.1), after buttoning down the ? download bitstream?, I want to make a bootloader from the external flash ,but a problem still baffles me all the time, when I pressed the ?program flash memory?, here is the context showed to me.. ------------- Performing CFI Query on the flash part(s)...Processor started. Type "st...

Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide"...

Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide" http://www.BurchED.com It is an easy step-by-step guide for FPGA beginners. I go all the way through from "What is an FPGA?" right up to compiling designs and downloading to your FPGA board There's a Free Membership area where you can watch some videos for free. ...

Hi, We are evaluating the interface to use for transferring data between an Altera/Xilinx FPGA and CPU. We are considering PCIe and GMII. This...

Hi, We are evaluating the interface to use for transferring data between an Altera/Xilinx FPGA and CPU. We are considering PCIe and GMII. This is going to be a point-to-point link with bi-directional data transfer hitting 500Mbps. The CPU we are using supports PCIe 1.1. My preference based on the research is to go for PCIe for the following reasons*. - High Throughput * PCIe 1.x at 2....